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ST STM32F0 Series Manuals
Manuals and User Guides for ST STM32F0 Series. We have
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ST STM32F0 Series manuals available for free PDF download: Programming Manual, Application Note
ST STM32F0 Series Programming Manual (91 pages)
Brand:
ST
| Category:
Microcontrollers
| Size: 0 MB
Table of Contents
Table 1. Applicable Products
1
Table of Contents
2
About this Document
8
Typographical Conventions
8
List of Abbreviations for Registers
8
About the STM32 Cortex-M0 Processor and Core Peripherals
9
Figure 1. STM32 Cortex-M0 Implementation
9
System Level Interface
10
Integrated Configurable Debug
10
Cortex-M0 Processor Features and Benefits Summary
10
Cortex-M0 Core Peripherals
10
The STM32 Cortex-M0 Processor
11
Programmers Model
11
Processor Modes
11
Stacks
11
Table 2. Summary of Processor Mode and Stack Usage
11
Core Registers
12
Table 3. Core Register Set Summary
12
Figure 2. Processor Core Registers
12
Table 4. PSR Register Combinations and Attributes
13
Figure 3. APSR, IPSR and EPSR Bit Assignments
13
Table 5. APSR Bit Definitions
14
Table 6. IPSR Bit Definitions
14
Table 7. EPSR Bit Definitions
15
Figure 4. PRIMASK Register Bit Assignments
15
Table 8. PRIMASK Register Bit Definitions
16
Table 9. CONTROL Register Bit Definitions
16
Figure 5. CONTROL Register Bit Assignments
16
Exceptions and Interrupts
17
Data Types
17
The Cortex Microcontroller Software Interface Standard (CMSIS)
17
Memory Model
18
Figure 6. Memory Map
18
Memory Regions, Types and Attributes
19
Memory System Ordering of Memory Accesses
19
Table 10. Ordering of Memory Accesses
19
Behavior of Memory Accesses
20
Software Ordering of Memory Accesses
20
Table 11. Memory Access Behavior
20
Memory Endianness
21
Figure 7. Little-Endian Example
21
Exception Model
22
Exception States
22
Exception Types
22
Exception Handlers
23
Table 12. Properties of the Different Exception Types
23
Vector Table
24
Figure 8. Vector Table
24
Exception Priorities
25
Exception Entry and Return
25
Figure 9. Cortex-M0 Stack Frame Layout
26
Table 13. Exception Return Behavior
27
Fault Handling
28
Power Management
28
Entering Sleep Mode
29
Wakeup from Sleep Mode
29
The External Event Input
30
Power Management Programming Hints
30
The STM32 Cortex-M0 Instruction Set
31
Instruction Set Summary
31
Table 14. Cortex-M0 Instructions
31
CMSIS Intrinsic Functions
35
Table 15. CMSIS Intrinsic Functions to Generate some Cortex-M0 Instructions
35
Table 16. CMSIS Intrinsic Functions to Access the Special Registers
35
About the Instruction Descriptions
36
Operands
36
Restrictions When Using PC or SP
36
Shift Operations
36
Figure 10. ASR#3
37
Figure 11. LSR#3
37
Figure 12. LSL#3
38
Figure 13. ROR #3
38
Address Alignment
39
PC-Relative Expressions
39
Conditional Execution
39
Table 17. Condition Code Suffixes and Their Relationship with the Flags
40
Memory Access Instructions
41
Table 18. Memory Access Instructions
41
Adr
42
LDR and STR, Immediate Offset
43
LDR and STR, Register Offset
44
LDR, PC-Relative
45
LDM and STM
46
PUSH and POP
47
General Data Processing Instructions
48
Table 19. Data Processing Instructions
48
ADD{S}, ADCS, SUB{S}, SBCS, and RSBS
49
Table 20. ADCS, ADD, RSBS, SBCS and SUB Operand Restrictions
50
ANDS, ORRS, EORS and BICS
51
ASRS, LSLS, LSRS and RORS
52
CMP and CMN
53
MOV, MOVS and MVNS
54
Muls
55
REV, REV16, and REVSH
56
SXTB, SXTH, UXTB and UXTH
57
Tst
58
Branch and Control Instructions
59
B, BL, BX, and BLX
59
Table 21. Branch and Control Instructions
59
Table 22. Branch Ranges
59
Miscellaneous Instructions
61
Bkpt
61
Table 23. Miscellaneous Instructions
61
Cpsid Cpsie
62
Dmb
63
Dsb
63
Isb
64
Mrs
64
Msr
65
Nop
66
Sev
66
Svc
67
Wfe
67
Wfi
68
Core Peripherals
69
About the STM32 Cortex-M0 Core Peripherals
69
Table 24. STM32 Core Peripheral Register Regions
69
Nested Vectored Interrupt Controller (NVIC)
70
Accessing the Cortex-M0 NVIC Registers Using CMSIS
70
Table 25. NVIC Register Summary
70
Table 26. CMSIS Access NVIC Functions
70
Interrupt Set-Enable Register (ISER)
71
Interrupt Clear-Enable Register (ICER)
71
Interrupt Set-Pending Register (ISPR)
72
Interrupt Clear-Pending Register (ICPR)
72
Interrupt Priority Register (IPR0-IPR7)
73
Table 27. IPR Bit Assignments
73
Figure 14. IPR Register Mapping
73
Level-Sensitive and Pulse Interrupts
74
NVIC Design Hints and Tips
75
Table 28. CMSIS Functions for NVIC Control
75
NVIC Register Map
76
Table 29. NVIC Register Map and Reset Values
76
System Control Block (SCB)
77
CPUID Base Register (CPUID)
77
Table 30. Summary of the System Control Block Registers
77
Interrupt Control and State Register (ICSR)
78
Application Interrupt and Reset Control Register (AIRCR)
80
System Control Register (SCR)
81
Configuration and Control Register (CCR)
82
System Handler Priority Registers (Shprx)
83
Table 31. System Fault Handler Priority Fields and Registers
83
SCB Usage Hints and Tips
84
SCB Register Map
84
Table 32. SCB Register Map and Reset Values
84
Systick Timer (STK)
85
Table 33. System Timer Registers Summary
85
Systick Control and Status Register (STK_CSR)
86
Systick Reload Value Register (STK_RVR)
87
Systick Current Value Register (STK_CVR)
87
Systick Calibration Value Register (STK_CALIB)
88
Table 34. Systick Register Map and Reset Values
89
Table 35. Document Revision History
90
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ST STM32F0 Series Application Note (52 pages)
Getting started with touch sensing control on STM32 microcontrollers
Brand:
ST
| Category:
Microcontrollers
| Size: 4 MB
Table of Contents
1 General Information
2
2 Terminology and Principle
3
Terminology
3
Principle
3
Table 1. Change Transfer Principle Documentation
4
Figure 1. Change Transfer Principle
4
3 Document Reference
5
Table 2. References Documentation
5
Figure 2. Main Documentation Tree
5
4 STM32L4 Touch Sensing Controller Online Presentation
6
Figure 3. STM32L4 Online Training
6
Figure 4. STM32L4 Touch Sensing Controller Online Training
6
5 Main Characteristics
7
Description
7
Signal Threshold
7
Figure 5. TSC Characteristics
7
Table 3. Signal Threshold Usage Documentation
8
Figure 6. Stmstudio Outputs
8
Charge Transfer
9
Table 4. Charge Transfer Documentation
9
Figure 7. Incomplete and Complete Charge Transfert Cycle
9
Sensitivity
10
Table 5. Sensitivity Documentation
10
Table 6. Dielectric Constants of Common Materials Used in a Panel Construction
10
Sensor
11
Key
11
Table 7. Key Documentation
11
Figure 8. Sensor Size
11
Linear or Slider
12
Table 8. Linear Touch Sensor Documentation
12
Figure 9. Interlaced Linear Touch Sensor with 3 Channels / 4 Electrodes (Half-Ended Electrodes Design)
12
Rotary or Wheel
13
Table 9. Rotary Sensor Documentation
13
Figure 10. Interlaced Patterned Rotary Sensor with 3 Channels / 3 Electrodes
13
Active Shield or Driven Shield
14
Table 10. Active Shield Documentation
14
Figure 11. Active Shield Principle
14
Layout and PCB
15
Led Rules
15
Table 11. Led Rules Documentation
15
Figure 12. Led Layout Example
15
Figure 13. Example of Cases Where a LED Bypass Capacitor Is Required
15
Electrode Not Located on PCB
16
Table 12. Electrode Documentation
16
Figure 14. Electrode Not Located on PCB Example
16
Ground, Shield and Sensors
17
Table 13. Layout Documentation
17
Figure 15. Hatched Ground and Signal Tracks
17
Figure 16. Ground Plane Example
17
Figure 17. Track Routing
18
Figure 18. Track Routing Recommendation
18
Figure 19. Shield
19
Faq
20
Noise
21
Power Supply
21
False Detection
21
Table 14. Power Supply Documentation
21
Table 15. False Detection Documentation
21
Figure 20. Typical Power Supply Schematic
21
Noise Immunity
22
Conducted Noise
22
Table 16. Noise Immunity Documentation
22
Table 17. Conducted Noise Documentation
22
6 Tuning
23
Table 18. Sensors Documentation
23
Table 19. ESD Documentation
23
Table 20. Conducted Noise Documentation
23
Table 21. Sampling Capacitor Documentation
23
7 Getting Started TSC with Stm32Cubemx
24
Uses Cases
24
Figure 21. Main Project Panel
24
Discovery Board: STM32F072B-DISCO
25
STM32F072B-DISCO Board Selection
25
Figure 22. STM32F072B-DISCO Board Selection
25
Figure 23. STM32F072B-DISCO Board Schematics
25
TSC Group and Sensor Activation
27
Figure 24. STM32F072B-DISCO Pinout SWD
27
Figure 25. STM32F072B-DISCO Pinout TSC
27
STM32F072B-DISCO Clock Tree
28
Figure 26. STM32F072B-DISCO Pinout Overview
28
Figure 27. STM32F072B-DISCO Clock Configuration
28
STM32F072B-DISCO Touchsensing Library
29
Figure 28. TOUCHSENSING Box Configuration
29
Figure 29. STM32F072B-DISCO Sensor Selection
29
Figure 30. STM32F072B-DISCO Sensor Selection Step2
30
Figure 31. STM32F072B-DISCO Sensor Selection Step3
30
Figure 32. STM32F072B-DISCO Sensor Selection Step4
31
Figure 33. STM32F072B-DISCO Sensor Selection Step5
31
STM32F072B-DISCO Software Project Generation
32
Figure 34. STM32F072B-DISCO Software Generation Step1
32
Figure 35. STM32F072B-DISCO Software Generation Step2
32
Figure 36. STM32F072B-DISCO Software Generation Step3
33
Figure 37. STM32F072B-DISCO IDE Workspace
33
Software Basic Algorythm
34
Figure 38. STM32F072B-DISCO Setup
35
Discovery Board: STM32L0538-DISCO
36
STM32L0538-DISCO Board Selection
36
Figure 39. STM32L0538-DISCO Board Selection
36
Figure 40. STM32L0538-DISCO Board Schematics
37
STM32L0538-DISCO TSC Group and Sensor Activation
38
Figure 41. Pinout SWD
38
Figure 42. Pinout TSC
38
STM32L0538-DISCO Clock Tree
39
Figure 43. Pinout Overview
39
Figure 44. Clock Configuration
39
STM32L0538-DISCO Touchsensing Library
40
Figure 45. TOUCHSENSING Box Configuration
40
Figure 46. STM32L0538-DISCO Sensor Selection Step1
40
Figure 47. STM32L0538-DISCO Sensor Selection Step2
41
Figure 48. STM32L0538-DISCO Sensor Selection Step3
41
Figure 49. STM32L0538-DISCO Sensor Selection Step4
42
Figure 50. STM32L0538-DISCO Sensor Selection Step5
42
STM32L0538-DISCO Software Project Generation
43
Figure 51. STM32L0538-DISCO Software Generation Step1
43
Figure 52. STM32L0538-DISCO Software Generation Step2
43
STM32L0538-DISCO Software Basic Algorythm
45
Revision History
46
Table 22. Document Revision History
46
ST STM32F0 Series Application Note (56 pages)
Brand:
ST
| Category:
Microcontrollers
| Size: 3 MB
Table of Contents
General Information
2
Table 2. Glossary
2
Overview
5
Security Purpose
5
Figure 1. Corrupted Connected Device Threat
5
Table 3. Assets to be Protected
6
Attack Types
7
Introduction to Attack Types
7
Software Attacks
8
Table 4. Attacks Types and Costs
8
Hardware Attacks
9
Non-Invasive Attacks
10
Silicon Invasive Attacks
11
Iot System Attack Examples
12
Figure 2. Iot System
12
List of Attack Targets
13
Device Protections
16
Configuration Protection
16
Trustzone ® for Armv8-M Architecture
16
Dual-Core Architecture
17
Figure 3. Armv8-M Trustzone® Execution Modes
17
Figure 4. Simplified Diagram of Dual-Core System Architecture
17
Memory Protections
18
Figure 5. Memory Types
18
System Flash Memory
19
User Flash Memory
19
Embedded SRAM
19
External Flash Memories
20
STM32 Memory Protections
21
Software Isolation
21
Debug Port and Other Interface Protection
21
Boot Protection
22
System Monitoring
22
Secure Applications
23
Secure Firmware Install (SFI)
23
Root and Chain of Trust
23
Stmicroelectronics Proprietary SBSFU Solution
23
Secure Boot (SB)
23
Secure Firmware Update (SFU)
24
Figure 6. Secure Boot FSM
24
Configurations
25
Arm TF-M Solution
25
Figure 7. Secure Server/Device SFU Architecture
25
Product Certifications
26
Table 8. Basic Feature Differences of Trustzone-Based Secure Software
26
STM32 Security Features
27
Overview of Security Features
27
Static and Dynamic Protections
27
Security Features by STM32 Devices
27
Table 10. Security Features for STM32L0/1/4/4+, STM32WB, STM32WL Devices
28
Readout Protection (RDP)
29
Table 11. Security Features for STM32L5, STM32U5, STM32H503/5, Stm32H72X/73/74X/75, Stm32H7Ax/7Bx, STM32F7 Devices
29
Figure 8. Example of RDP Protections (STM32L4 Series)
30
Lifecycle Management-Product State
31
Table 12. RDP Protections
31
One-Time Programmable (OTP)
32
Trustzone
32
Core State
33
Secure Attribution Unit (SAU)
33
Figure 9. Trustzone® Implementation at System Level
33
Memory and Peripheral Protections
34
Flash Memory Write Protection (WRP)
34
Execute-Only Firmware (PCROP)
34
Secure Hide Protection (HDP)
35
Firewall
35
Figure 10. HDP Protected Firmware Access
35
Figure 11. Firewall FSM
36
Figure 12. Firewall Application Example
36
Memory Protection Unit (MPU)
37
Table 13. Attributes and Access Permission Managed by MPU
37
Customer Key Storage (CKS)
38
Table 14. Process Isolation
38
Figure 13. Dual-Core Architecture with CKS Service
38
Antitamper (Tamp)/Backup Registers (BKP)
39
Clock Security System (CSS)
39
Power Monitoring (PVD)
39
Memory Integrity Hardware Check
39
Independent Watchdog (IWDG)
40
Device ID
40
Cryptography
40
Hardware Accelerators
40
Cryptolib Software Library
40
On-The-Fly Decryption Engine (OTFDEC)
41
Figure 14. Typical OTFDEC Configuration
41
Guidelines
42
Table 15. Security Use Cases
42
Conclusion
44
Appendix A Cryptography - Main Concepts
45
Secret Key Algorithms
45
Figure 15. Symmetric Cryptography
45
Public Key Algorithms (PKA)
46
Figure 16. Signature
46
Figure 17. PKA Encryption
46
Hash Algorithms
47
MAC or Signature and Certificate
47
Figure 18. Message Hashing
47
Figure 19. MAC Generation with Secrete Key Algorithm
47
Figure 20. Signature Generation with Public Key Algorithm
48
Revision History
49
Table 1. Applicable Products
49
Table 16. Document Revision History
49
Table 5. Memory Types and Associated Protection
50
Table 6. Scope of STM32 Embedded Memory Protection Features
50
Table 7. Software Isolation Mechanism
50
Table 9. Security Features for STM32C0, STM32F0/1/2/3/4, STM32G0/4 Devices
50
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ST STM32F0 Series Application Note (29 pages)
Brand:
ST
| Category:
Microcontrollers
| Size: 0 MB
Table of Contents
Table of Contents
2
Power Supplies of the Stm32F05Xxx Family
4
Power Supply Schemes
4
Independent Analog Converter Supply
5
Battery Backup
5
Voltage Regulator
5
Reset and Power Supply Supervisor
7
Power-On Reset (POR) / Power-Down Reset (PDR)
7
System Reset
8
Programmable Voltage Detector (PVD)
10
Power Supplies of the Stm32F06Xxx Family
11
Power Supply Schemes
11
Independent Analog Converter Supply
12
Battery Backup
12
Reset and Power Supply Supervisor
13
External Power-On Reset and Power-Down Reset (NPOR)
13
System Reset
13
Clocks
15
High Speed External Clock Signal (HSE) OSC Clock
15
LSE Clock
16
HSI Clock
16
LSI Clock
17
ADC Clock
17
Clock Security System (CSS)
17
Boot Configuration
18
Debug Management
19
Introduction
19
SWD Port (Serial Wire Debug)
19
Pinout and Debug Port Pins
19
Serial Wire Debug (SWD) Pin Assignment
19
SWD Pin Assignment
20
Internal Pull-Up and Pull-Down on SWD Pins
20
SWD Port Connection with Standard SWD Connector
20
Recommendations
21
Printed Circuit Board
21
Component Position
21
Ground and Power Supply (VSS , VDD , VDDA )
21
Decoupling
21
Other Signals
22
Unused I/Os and Features
22
Reference Design
23
Description
23
Clock
23
Reset
23
Stm32F06Xxx Power-On Reset
23
Boot Mode
23
SWD Interface
23
Power Supply
23
Pinouts and Pin Description
24
Component References
24
Hardware Migration from STM32F1 to STM32F0
27
Revision History
28
ST STM32F0 Series Application Note (17 pages)
Clock configuration too
Brand:
ST
| Category:
Microcontrollers
| Size: 0 MB
Table of Contents
Table of Contents
2
Glossary
5
Getting Started
6
Software Requirements
6
Hardware Requirements
7
Introduction
7
Clock Scheme for Stm32F0Xx Microcontrollers
7
Figure 1. Clock Scheme
8
I2S Clock Generator
9
Figure 2. I2S Clock Generator Architecture
9
Tutorials
10
Wizard Mode
10
Figure 3. Wizard Mode User Interface
10
Figure 4. Select the Clock Source
11
Figure 5. File Generation Error
11
Expert Mode
12
Figure 6. Expert Mode User Interface
12
Figure 7. System Clock Frequency Is Exceeded
13
Known Limitations
14
Conclusion
15
Revision History
16
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