Independent Lcd Supply (Stm32L0X3 Only); Voltage Regulator; Table 2. Vlcd Rails Connections To Gpio Pins - ST STM32L0 Series Application Note

AN4467
1.1.2

Independent LCD supply (STM32L0x3 only)

The V
LCD
two ways:
•
It can receive, from an external circuitry, the desired maximum voltage that is provided
on the segment and common lines to the glass LCD by the microcontroller.
•
It can also be used to connect an external capacitor that is used by the microcontroller
for its voltage step-up converter. This step-up converter is controlled by software to
provide the desired voltage to the segment and common lines of the glass LCD. Refer
to the specific product datasheet for the capacitor value.
The voltage provided to the segment and common lines defines the contrast of the glass
LCD pixels. This contrast can be reduced when the dead time between frames is
configured.
In case of LCD with big pixel, the high capacitance of the pixel might degrade the LCD
signal shape. So the device offer the possibility to connect internal VLCD rails
(LCD_VLCD1, LCD_VLCD2, LCD_VLCD3) to optional capacitors. This improves the
Segment and Common line signals shape with limited use of high drive resistor network, so
it improves the signal shape without extra current consumption. The values of these
decoupling capacitors must be tuned accordingto the LCD glass and the PCB capacitances.
As a guideline the user can set the decoupling capacitor values to approximately 10 times
the LCD and PCB capacitance. The LCD rails to be connected depends on the Bias
configuration.
LCD_VLCD3
LCD_VLCD2
LCD_VLCD1
1.1.3

Voltage regulator

The internal voltage regulator is always enabled after reset. It can be configured to provide
the core with three different voltage ranges. Choosing a range with low V
consumption but lowers the maximum acceptable core speed. Consumption ranges in
decreasing consumption order are as follows:
•
Range 1, available only for V
•
Range 2 allows CPU frequency up to 16 MHz
•
Range 3 allows CPU frequency up to 4 MHz
Note: In Range 1, when VDD is below 2.0V, the CPU frequency in run mode must be managed to
prevent any changes exceeding a ratio of 4 in one shot. A delay of 5µs must be respected
between 2 changes. There is no limitation when waking up from low-power mode.
pin is provided to control the contrast of the glass LCD. This pin can be used in

Table 2. VLCD rails connections to GPIO pins

1/2
Not used
1/2 V
LCD
Not used
DocID026156 Rev 1
Bias
1/3
Not used
2/3 V
LCD
1/3 V
LCD
above 1.71 V, allows maximum speed
DD
Power supplies
Pin selected by
CAPA[2:0] bits
1/4
3/4 V PB0
LCD
1/2 V PB2
LCD
1/2 V PB12
LCD
reduces the
core
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