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Motorola MC68020 User Manual

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Page 2 Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur.
Page 3 MC68020 32-bit, second-generation, enhanced microprocessor and the MC68EC020 32- bit, second-generation, enhanced embedded microprocessor. Throughout this manual, “MC68020/EC020” is used when information applies to both the MC68020 and the MC68EC020. “MC68020” and “MC68EC020” are used when information applies only to the MC68020 or MC68EC020, respectively.
Page 4 Section 3 Signal Description Signal Index .................... 3-2 Function Code Signals (FC2–FC0) ............3-2 Address Bus (A31–A0, MC68020)(A23–A0, MC68EC020) ....3-2 Data Bus (D31–D0) ................. 3-2 Transfer Size Signals (SIZ1, SIZ0) ............3-2 Asynchronous Bus Control Signals ............3-4 Interrupt Control Signals................3-5 Bus Arbitration Control Signals ...............
Page 5 5.4.1.2 Autovector Interrupt Acknowledge Cycle ......... 5-48 5.4.1.3 Spurious Interrupt Cycle ..............5-48 5.4.2 Breakpoint Acknowledge Cycle ............5-50 5.4.3 Coprocessor Communication Cycles ..........5-53 Bus Exception Control Cycles..............5-53 5.5.1 Bus Errors ................... 5-55 viii M68020 USER’S MANUAL MOTOROLA...
Page 6 MC68020 Bus Arbitration ..............5-63 5.7.1.1 Bus Request (MC68020) ..............5-66 5.7.1.2 Bus Grant (MC68020) ..............5-66 5.7.1.3 Bus Grant Acknowledge (MC68020) ..........5-66 5.7.1.4 Bus Arbitration Control (MC68020) ..........5-67 5.7.2 MC68EC020 Bus Arbitration ............... 5-70 5.7.2.1 Bus Request (MC68EC020) ............5-71 5.7.2.2...
Page 7 7.2.3.3 Coprocessor Context Save Instruction ..........7-20 7.2.3.3.1 Format ..................7-20 7.2.3.3.2 Protocol ..................7-21 7.2.3.4 Coprocessor Context Restore Instruction ........7-22 7.2.3.4.1 Format ..................7-22 7.2.3.4.2 Protocol ..................7-23 Coprocessor Interface Register Set ............7-24 M68020 USER’S MANUAL MOTOROLA...
Page 8 Coprocessor-Detected Illegal Command or Condition Words ..7-51 7.5.1.3 Coprocessor Data-Processing-Related Exceptions ......7-51 7.5.1.4 Coprocessor System-Related Exceptions ........7-51 7.5.1.5 Format Errors ................... 7-52 7.5.2 Main-Processor-Detected Exceptions ..........7-52 7.5.2.1 Protocol Violations ................7-52 7.5.2.2 F-Line Emulator Exceptions ............. 7-54 MOTOROLA M68020 USER’S MANUAL...
Page 9 Control Instructions................8-38 8.2.17 Exception-Related Instructions ............8-39 8.2.18 Save and Restore Operations ............. 8-40 Section 9 Applications Information Floating-Point Units ................. 9-1 Byte Select Logic for the MC68020/EC020..........9-5 Power and Ground Considerations ............9-9 M68020 USER’S MANUAL MOTOROLA...
Page 10 Standard MC68020 Ordering Information.......... 11-1 11.1.2 Standard MC68EC020 Ordering Information ........11-1 11.2 Pin Assignments and Package Dimensions .......... 11-2 11.2.1 MC68020 RC and RP Suffix—Pin Assignment ......... 11-2 11.2.2 MC68020 RC Suffix—Package Dimensions ........11-3 11.2.3 MC68020 RP Suffix—Package Dimensions........11-4 11.2.4 MC68020 FC and FE Suffix—Pin Assignment ........
Page 11 Relationship between External and Internal Signals........5-2 Input Sample Window ..................5-2 Internal Operand Representation ..............5-6 MC68020/EC020 Interface to Various Port Sizes ..........5-6 Long-Word Operand Write to Word Port Example........... 5-10 Long-Word Operand Write to Word Port Timing ..........5-11 Word Operand Write to Byte Port Example .............
Page 12 Halt Operation Timing ..................5-61 5-42 MC68020 Bus Arbitration Flowchart for Single Request ........5-64 5-43 MC68020 Bus Arbitration Operation Timing for Single Request ...... 5-65 5-44 MC68020 Bus Arbitration State Diagram ............5-67 5-45 MC68020 Bus Arbitration Operation Timing—Bus Inactive ......5-69 5-46 MC68EC020 Bus Arbitration Flowchart for Single Request ......
Page 13 Page Number Title Number Coprocessor Address Map in MC68020/EC020 CPU Space ......7-7 Coprocessor Interface Register Set Map ............7-7 Coprocessor General Instruction Format (cpGEN) .......... 7-8 Coprocessor Interface Protocol for General Category Instructions....7-10 Coprocessor Interface Protocol for Conditional Category Instructions .... 7-11 Branch on Coprocessor Condition Instruction Format (cpBcc.W) ....
Page 14 Chip Select Generation PAL ................9-3 Chip Select PAL Equations ................9-4 Bus Cycle Timing Diagram ................9-4 Example MC68020/EC020 Byte Select PAL System Configuration ....9-7 MC68020/EC020 Byte Select PAL Equations ..........9-8 High-Resolution Clock Controller ..............9-11 Alternate Clock Solution ................... 9-11 Access Time Computation Diagram ..............
Page 15 SIZ1, SIZ0 Signal Encoding ................5-7 Address Offset Encodings ................5-7 Data Bus Requirements for Read Cycles ............5-8 MC68020/EC020 Internal to External Data Bus Multiplexer— Write Cycles ....................5-9 Memory Alignment and Port Size Influence on Read/Write Bus Cycles ..5-20 Data Bus Byte Enable Signals for Byte, Word, and Long-Word Ports .....
Page 16 AVDV Less Than or Equal to the CPU Maximum Frequency Rating......9-14 Access Status Register Codes................. 9-18 θ 10-1 vs. Airflow—MC68020 CQFP Package ........... 10-3 10-2 Power vs. Rated Frequency (at T Maximum = 110°C) ......... 10-3 10-3 Temperature Rise of Board vs. P —MC68020 CQFP Package ....
Page 17 MC68020/EC020 ACRONYM LIST BCD — Binary-Coded Decimal CAAR — Cache Address Register CACR — Cache Control Register CCR — Condition Code Register CIR — Coprocessor Interface Register CMOS — Complementary Metal Oxide Semiconductor CPU — Central Processing Unit CQFP — Ceramic Quad Flat Pack DDMA —...
Page 18 The MC68EC020 is an economical high-performance embedded microprocessor based on the MC68020 and has been designed specifically to suit the needs of the embedded microprocessor market. The major differences in the MC68EC020 and the MC68020 are that the MC68EC020 has a 24-bit address bus and does not implement the following signals: ECS , OCS , DBEN , IPEND , and BGACK .
Page 19 • 4-Gbyte Direct Addressing Range for the MC68020 • 16-Mbyte Direct Addressing Range for the MC68EC020 • Selection of Processor Speeds for the MC68020: 16.67, 20, 25, and 33.33 MHz • Selection of Processor Speeds for the MCEC68020: 16.67 and 25 MHz A block diagram of the MC68020/EC020 is shown in Figure 1-1.
Page 20 ADDRESS SIZE ADDRESS COUNTER SECTION SECTION MULTIPLEXER PADS SECTION ADDRESS MISALIGNMENT MULTIPLEXER BUS CONTROLLER WRITE PENDING PREFETCH PENDING BUFFER BUFFER MICROBUS CONTROL LOGIC BUS CONTROL SIGNALS 24-Bit for MC68EC020 Figure 1-1. MC68020/EC020 Block Diagram MOTOROLA M68020 USER’S MANUAL 1- 3...
Page 21 1.2 PROGRAMMING MODEL The programming model of the MC68020/EC020 consists of two groups of registers, the user model and the supervisor model, that correspond to the user and supervisor privilege levels, respectively. User programs executing at the user privilege level use the registers of the user model.
Page 22 DATA REGISTERS ADDRESS REGISTERS USER STACK A7 (USP) POINTER PROGRAM COUNTER CONDITION CODE REGISTER Figure 1-2. User Programming Model MOTOROLA M68020 USER’S MANUAL 1- 5...
Page 23 INTERRUPT STACK A7' (ISP) POINTER MASTER STACK A7'' (MSP) POINTER STATUS (CCR) REGISTER VECTOR BASE REGISTER ALTERNATE FUNCTION CODE REGISTERS CACHE CONTROL CACR REGISTER CACHE ADDRESS CAAR REGISTER Figure 1-3. Supervisor Programming Model Supplement 1- 6 M68020 USER’S MANUAL MOTOROLA...
Page 24 The alternate function code registers, SFC and DFC, contain 3-bit function codes. For the MC68020, function codes can be considered extensions of the 32-bit linear address that optionally provide as many as eight 4-Gbyte address spaces; for the MC68EC020, function codes can be considered extensions of the 24-bit linear address that optionally provide as many as eight 16-Mbyte address spaces.
Page 25 6. Long-Word Integers (32 bits) 7. Quad-Word Integers (64 bits) In addition, the MC68020/EC020 instruction set supports operations on other data types such as memory addresses. The coprocessor mechanism allows direct support of floating- point operations with the MC68881 and MC68882 floating-point coprocessors as well as specialized user-defined data types and functions.
Page 26 16 or 32 bits. Program Counter <data> = Immediate value of 8, 16, or 32 bits ( ) = Effective Address Use as indirect access to long-word address. MOTOROLA M68020 USER’S MANUAL 1- 9...
Page 27 18 addressing modes. 1.5 VIRTUAL MEMORY AND VIRTUAL MACHINE CONCEPTS The full addressing range of the MC68020 is 4 Gbytes (4,294,967,296 bytes) in each of eight address spaces; the full addressing range of the MC68EC020 is 16 Mbytes (16,777,216 bytes) in each of the eight address spaces.
Page 28 MOVE Move cpRESTORE Restore Internal State of Coprocessor MOVEA Move Address cpSAVE Save Internal State of Coprocessor MOVE CCR Move Condition Code Register cpScc Set Conditionally MOVE SR Move Status Register cpTRAPcc Trap Conditionally MOTOROLA M68020 USER’S MANUAL 1- 11...
Page 29 (and should be emulated) are trapped to the governing operating system and performed by its software. In the MC68020/EC020 implementation of a virtual machine, the virtual application runs at the user privilege level. The governing operating system executes at the supervisor...
Page 30 Additionally, instructions that reside in proximity to the instructions currently in use also have a high probability of being utilized within a short period. To exploit these locality characteristics, the MC68020/EC020 contains an on-chip instruction cache.
Page 31 For example, if during the exception processing of one bus error another bus error occurs, the MC68020/EC020 has not completed the transition to normal processing and has not completed saving the internal state of the machine; therefore, the processor assumes that the system is not operational and halts.
Page 32 ISP, can be used for interrupt control information and workspace area as interrupt handling routines require. When the M-bit is clear, the MC68020/EC020 is in the interrupt mode of the supervisor privilege level, and operation is the same as supervisor mode in the MC68000, MC68HC001, MC68008, and MC68010.
Page 33 After these instructions execute, the instruction pipeline is flushed and is refilled from the appropriate address space. The RTE instruction returns to the program that was executing when the exception occurred. It restores the exception stack frame saved on the supervisor stack. If the frame MOTOROLA M68020 USER’S MANUAL 2- 3...
Page 34 Table 2-1 lists the types of accesses defined for the MC68020/EC020 and the corresponding values of the FC2–FC0 signals. Table 2-1. Address Space Encodings...
Page 35 Details of exception processing are provided in Section 6 Exception Processing, and Table 6-1 lists the exception vector assignments. MOTOROLA M68020 USER’S MANUAL 2- 5...
Page 36 Processing for a complete list of exception stack frames. STATUS REGISTER PROGRAM COUNTER FORMAT VECTOR OFFSET ADDITIONAL PROCESSOR STATE INFORMATION (2, 6, 12, OR 42 WORDS, IF NEEDED) Figure 2-1. General Exception Stack Frame 2- 6 M68020 USER’S MANUAL MOTOROLA...
Page 37 ADDRESS BUS A31–A0 IPL2 INTERRU CONTRO DATA BUS D31–D0 IPEND SIZ0 AVEC TRANSFER SIZE SIZ1 BUS ARB CONTRO BGACK MC68020 RESET HALT BUS EXC ASYNCHRONOUS CONTRO BUS CONTROL BERR DBEN DSACK0 DSACK1 CDIS EMULATOR SUPPORT Figure 3-1. Functional Signal Groups MOTOROLA M68020 USER’S MANUAL...
Page 38 These three-state bidirectional signals provide the general-purpose data path between the MC68020/EC020 and all other devices. The data bus can transfer 8, 16, 24, or 32 bits of data per bus cycle. D31 is the most significant bit of the data bus. Refer to Section 5 Bus Operation for more information on the data bus and its relationship to bus operation.
Page 39 Statically disables the on-chip cache to assist emulator support. Clock Clock input to the processor. Power Supply Power supply. Ground Ground connection. This signal is implemented in the MC68020 and not implemented in the MC68EC020. MOTOROLA M68020 USER’S MANUAL 3- 3...
Page 40 During a write cycle, DS indicates that the MC68020/EC020 has placed valid data on the bus. During two-clock synchronous write cycles, the MC68020/EC020 does not assert DS . Refer to Section 5 Bus Operation for more information about the relationship of DS to bus operation.
Page 41 Operation for more information on these signals and their relationship to dynamic bus sizing. 3.7 INTERRUPT CONTROL SIGNALS The following signals are the interrupt control signals for the MC68020/EC020. Note that IPEND is implemented in the MC68020 and not implemented in the MC68EC020. Interrupt Priority Level Signals (IPL2–IPL0) These input signals provide an indication of an interrupt condition and the encoding of the interrupt level from a peripheral or external prioritizing circuitry.
Page 42 3.8 BUS ARBITRATION CONTROL SIGNALS The following signals are the bus arbitration control signals used to determine which device in a system is the bus master. Note that BGACK is implemented in the MC68020 and not implemented in the MC68EC020.
Page 43 CDIS is negated. 3.11 CLOCK (CLK) The CLK signal is the clock input to the MC68020/EC020. This TTL-compatible signal should not be gated off at any time while power is applied to the processor. Refer to Section 9 Applications Information for suggestions on clock generation. Refer to Section 10 Electrical Characteristics for electrical characteristics.
Page 44 3.13 SIGNAL SUMMARY Table 3-2 provides a summary of the characteristics of the signals discussed in this section. Signal names preceded by an asterisk (*) are implemented in the MC68020 and not implemented in the MC68EC020. Table 3-2. Signal Summary...
Page 45 SECTION 4 ON-CHIP CACHE MEMORY The MC68020/EC020 incorporates an on-chip cache memory as a means of improving performance. The cache is implemented as a CPU instruction cache and is used to store the instruction stream prefetch accesses from the main memory.
Page 46 COMPARATOR LINE Figure 4-1. MC68020/EC020 On-Chip Cache Organization When an instruction fetch occurs, the cache (if enabled) is first checked to determine if the word required is in the cache. This check is achieved by first using the index field (A7–A2) of the access address as an index into the on-chip cache.
Page 47 CACR are also cleared. 4.3 CACHE CONTROL Only the MC68020/EC020 cache control circuitry can directly access the cache array, but a supervisor program can set bits in the CACR to exercise control over cache operations. The supervisor level also has access to the CAAR, which contains the address for a cache entry to be cleared.
Page 48 RESERVED Figure 4-3. Cache Address Register Bits 31–8, 1, and 0—Reserved These bits are reserved for use by Motorola. Index Field The index field contains the address for the “clear cache entry” operations. The bits of this field, which correspond to A7–A2, specify the index and a long word of a cache line.
Page 49 MC68020/EC020 clock, introducing a delay. This delay is the time period required for the MC68020/EC020 to sample an input signal, synchronize the input to the internal clocks of the processor, and determine whether the MOTOROLA M68020 USER’S MANUAL...
Page 50 The MC68020/EC020 initiates a bus cycle by driving the A1–A0, SIZ1, SIZ0, FC2–FC0, and R/W outputs. However, if the MC68020/EC020 finds the required instruction in the on- chip cache, the processor aborts the cycle before asserting the AS.The assertion of AS ensures that the cycle has not been aborted by these internal conditions.
Page 51 When initiating a bus cycle, the MC68020 asserts ECS in addition to A1–A0, SIZ1, SIZ0, FC2–FC0, and R/W . ECS can be used to initiate various timing sequences that are eventually qualified with AS. Qualification with AS may be required since, in the case of an internal cache hit, a bus cycle may be aborted after ECS has been asserted.
Page 52 AS during a write cycle. 5.1.6 Data Buffer Enable The MC68020 DBEN signal is used to enable external data buffers while data is present on the data bus. During a read operation, DBEN is asserted one clock cycle after the beginning of the bus cycle and is negated as DS is negated.
Page 53 (Refer to 5.2.2 Misaligned Operands for the case of a word or byte address.) If the port responds that it is 32 bits wide, the MC68020/EC020 latches all 32 bits of data and continues with the next operation. If the port responds that it is 16 bits wide, the MC68020/EC020 latches the 16 bits of valid data and runs another bus cycle to obtain the other 16 bits.
Page 54 BYTE OPERAND Figure 5-3. Internal Operand Representation Figure 5-4 shows the required organization of data ports on the MC68020/EC020 bus for 8-, 16-, and 32-bit devices. The four bytes shown in Figure 5-4 are connected through the internal data bus and data multiplexer to the external data bus. This path is the means through which the MC68020/EC020 supports dynamic bus sizing and operand misalignment.
Page 55 A1–A0 also affect operation of the data multiplexer. During an operand transfer, A31–A2 (for the MC68020) or A23–A2 (for the MC68EC020) indicate the long-word base address of that portion of the operand to be accessed; A1 and A0 indicate the byte offset from the base.
Page 56 Byte Port Long-Word Port Word Port Transfer External Size Address External Data Bytes External Data Bytes Size Data Bytes Required Required Required SIZ1 SIZ0 D31–D24 D23–D16 D15–D8 D7–D0 D31–D24 D23–D16 D31–D24 Byte Word 3 Bytes Long Word M68020 USER’S MANUAL MOTOROLA...
Page 57 Table 5-5 lists the combinations of SIZ1, SIZ0, A1, and A0 and the corresponding pattern of the data transfer for write cycles from the internal multiplexer of the MC68020/EC020 to the external data bus. Table 5-5. MC68020/EC020 Internal to External Data Bus Multiplexer—Write Cycles...
Page 58 Figure 5-5 shows the transfer (write) of a long-word operand to a word port. In the first bus cycle, the MC68020/EC020 places the four operand bytes on the external bus. Since the address is long-word aligned in this example, the multiplexer follows the pattern in the entry of Table 5-5 corresponding to SIZ0, SIZ1, A0, A1 = 0000.
Page 59 DBEN D31–D24 D23–D16 WORD WRITE WORD WRITE LONG-WORD OPERAND WRITE TO 16-BIT PORT For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020. Figure 5-6. Long-Word Operand Write to Word Port Timing MOTOROLA M68020 USER’S MANUAL 5- 11...
Page 60 Figure 5-8 shows the associated bus transfer signal timing. WORD OPERAND D31 DATA BUS D24 BYTE MEMORY MC68020/EC020 MEMORY CONTROL SIZ1 SIZ0 A1 DSACK1 DSACK0 Figure 5-7. Word Operand Write to Byte Port Example 5-12 M68020 USER’S MANUAL...
Page 61 DSACK0 DBEN D31–D24 D23–D16 D15–D8 D7–D0 BYTE WRITE BYTE WRITE WORD OPERAND WRITE For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020. Figure 5-8. Word Operand Write to Byte Port Timing MOTOROLA M68020 USER’S MANUAL 5- 13...
Page 62 MC68000, MC68008, and MC68010 implementations allow long-word transfers on odd- word boundaries but force exceptions if word or long-word operand transfers are attempted at odd-byte addresses. Although the MC68020/EC020 does not enforce any alignment restrictions for data operands (including PC relative data addresses), some performance degradation occurs when additional bus cycles are required for long-word or word operands that are misaligned.
Page 63 D23–D16 D15–D8 D7–D0 BYTE WRITE WORD WRITE BYTE WRITE LONG-WORD OPERAND WRITE For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020. Figure 5-10. Misaligned Long-Word Operand Write to Word Port Timing MOTOROLA M68020 USER’S MANUAL 5- 15...
Page 64 LONG-WORD OPERAND (REGISTER) DATA BUS MEMORY CONTROL WORD MEMORY MC68020/EC020 SIZ1 SIZ0 A2 DSACK1 DSACK0 Figure 5-11. Misaligned Long-Word Operand Read from Word Port Example Figures 5-12 and 5-13 show a word transfer (write) to an odd address in word-organized memory.
Page 65 WORD WRITE BYTE WRITE WORD OPERAND WRITE TO A1, A0 = 01 For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020. Figure 5-13. Misaligned Word Operand Write to Word Port Timing MOTOROLA M68020 USER’S MANUAL 5- 17...
Page 66 WORD OPERAND (REGISTER) DATA BUS WORD MEMORY MC68020/EC020 MEMORY CONTROL SIZ1 SIZ0 A2 DSACK1 DSACK0 Figure 5-14. Misaligned Word Operand Read from Word Bus Example Figures 5-15 and 5-16 show an example of a long-word transfer (write) to an odd address in long-word-organized memory.
Page 67 DBEN D31–D24 D23–D16 D15–D8 D7–D0 BYTE WRITE 3-BYTE WRITE LONG-WORD OPERAND WRITE For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020. Figure 5-16. Misaligned Long-Word Operand Write to Long-Word Port Timing MOTOROLA M68020 USER’S MANUAL 5- 19...
Page 68 Instruction prefetches are always two words from a long-word boundary Table 5-6 reveals that bus cycle throughput is significantly affected by port size and alignment. The MC68020/EC020 system designer and programmer should be aware of and account for these effects, particularly in time-critical applications.
Page 69 A dash (—) implies that the byte enable signal does not apply. The MC68020/EC020 always drives all sections of the data bus because, at the beginning of a write cycle, the bus controller does not know the port size.
Page 70 AS is not asserted. For the MC68020, if the bus is not occupied with another read or write cycle, the bus controller asserts the ECS signal (and the OCS signal, if appropriate). It is possible to have ECS asserted on multiple consecutive clock cycles.
Page 71 UPPER MIDDLE DATA (32-BIT PORT) LOWER MIDDLE DATA (32-BIT PORT) SIZ1 LOWER LOWER DATA (32-BIT PORT) UPPER DATA (16-BIT PORT) LOWER DATA (16-BIT PORT) Figure 5-18. Byte Enable Signal Generation for 16- and 32-Bit Ports MOTOROLA M68020 USER’S MANUAL 5- 23...
Page 72 5.2.6 Bus Operation The MC68020/EC020 bus is used in an asynchronous manner allowing external devices to operate at clock frequencies different from the MC68020/EC020 clock. Bus operation uses the handshake lines (AS, DS, DSACK0, DSACK1, BERR, and HALT) to control data transfers.
Page 73 In addition, the bus master is responsible for de-skewing DSACK1/DSACK0, D31–D0, BERR, HALT, and, for the MC68020, DBEN from the slave devices. The following paragraphs define read, write, and read-modify-write cycle operations.
Page 74 During a read cycle, the processor receives data from a memory, coprocessor, or peripheral device. If the instruction specifies a long-word operation, the MC68020/EC020 attempts to read four bytes at once. For a word operation, it attempts to read two bytes at once and for a byte operation, one byte.
Page 75 3) NEGATE DBEN TERMINATE CYCLE 1) REMOVE DATA FROM D31–D0 2) NEGATE DSACK1/DSACK0 START NEXT CYCLE This step does not apply to the MC68EC020. For the MC68EC020, A23–A0. Figure 5-20. Byte Read Cycle Flowchart MOTOROLA M68020 USER’S MANUAL 5- 27...
Page 76 A31–A2 FC2–FC0 SIZ1 WORD BYTE SIZ0 DSACK1 DSACK0 DBEN D31–D24 D23–D16 D15–D8 D7–D0 WORD READ BYTE READ BYTE READ Figure 5-21. Byte and Word Read Cycles—32-Bit Port 5-28 M68020 USER’S MANUAL MOTOROLA...
Page 77 D23–D16 D15–D8 D7–D0 BYTE READ BYTE READ BYTE READ BYTE READ LONG-WORD OPERAND READ FROM 8-BIT PORT For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020. Figure 5-22. Long-Word Read—8-Bit Port MOTOROLA M68020 USER’S MANUAL 5- 29...
Page 78 D7–D0 LONG-WORD READ WORD READ WORD READ FROM 32-BIT PORT LONG-WORD OPERAND READ FROM 16-BIT PORT For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020. Figure 5-23. Long-Word Read—16- and 32-Bit Ports 5-30 M68020 USER’S MANUAL MOTOROLA...
Page 79 State 0 MC68020—The read cycle starts in state 0 (S0). The processor asserts ECS, indicating the beginning of an external cycle. If the cycle is the first external cycle of a read operation, OCS is asserted simultaneously. During S0, the processor places a valid address on A31–A0 and valid function codes on FC2–FC0.
Page 80 MC68020/EC020—At the end of state 4 (S4), the processor latches the incoming data. State 5 MC68020—The processor negates AS, DS, and DBEN during state 5 (S5). It holds the address valid during S5 to provide address hold time for memory systems. R/W, SIZ1–...
Page 81 1) NEGATE AS AND DS 2) REMOVE DATA FROM D31–D0 TERMINATE CYCLE 3) NEGATE DBEN 1) NEGATE DSACK1/DSACK0 START NEXT CYCLE This step does not apply to the MC68EC020. For the MC68EC020, A23–A0. Figure 5-24. Write Cycle Flowchart MOTOROLA M68020 USER’S MANUAL 5- 33...
Page 82 A31–A2 FC2–FC0 SIZ1 LONG WORD SIZ0 DSACK1 DSACK0 DBEN D31–D0 BYTE READ WRITE WRITE READ WITH WAIT STATES For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020. Figure 5-25. Read-Write-Read Cycles—32-Bit Port 5-34 M68020 USER’S MANUAL MOTOROLA...
Page 83 SIZ0 DSACK1 DSACK0 DBEN D31–D24 D23–D16 D15–D8 D7–D0 WORD WRITE BYTE WRITE BYTE WRITE For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020. Figure 5-26. Byte and Word Write Cycles—32-Bit Port MOTOROLA M68020 USER’S MANUAL 5- 35...
Page 84 D23–D16 D15–D8 D7–D0 BYTE WRITE BYTE WRITE BYTE WRITE BYTE WRITE LONG-WORD OPERAND WRITE TO 8-BIT PORT For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020. Figure 5-27. Long-Word Operand Write—8-Bit Port 5-36 M68020 USER’S MANUAL MOTOROLA...
Page 85 D7–D0 WORD WRITE WORD WRITE LONG-WORD WRITE TO 32-BIT PORT LONG-WORD OPERAND WRITE TO 16-BIT PORT For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020. Figure 5-28. Long-Word Operand Write—16-Bit Port MOTOROLA M68020 USER’S MANUAL 5- 37...
Page 86 State 0 MC68020—The write cycle starts in S0. The processor negates ECS, indicating the beginning of an external cycle. If the cycle is the first external cycle of a write operation, OCS is asserted simultaneously. During S0, the processor places a valid address on A31–A0 and valid function codes on FC2–FC0.
Page 87 5.3.3 Read-Modify-Write Cycle The read-modify-write cycle performs a read, conditionally modifies the data in the arithmetic logic unit, and may write the data out to memory. In the MC68020/EC020, this operation is indivisible, providing semaphore capabilities for multiprocessor systems. During the entire read-modify-write sequence, the MC68020/EC020 asserts RMC to indicate that an indivisible operation is occurring.
Page 88 TERMINATE CYCLE D ; ELSE GO TO E 1) NEGATE DSACK1/DSACK0 UNLOCK BUS 1) NEGATE RMC START NEXT CYCLE This step does not apply to the MC68EC020. For the MC68EC020, A23–A0. Figure 5-29. Read-Modify-Write Cycle Flowchart 5-40 M68020 USER’S MANUAL MOTOROLA...
Page 89 SIZ0 DSACK1 DSACK0 DBEN D31–D24 D23–D16 D15–8 D7–D0 BERR HALT INDIVISIBLE CYCLE NEXT CYCLE For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020. Figure 5-30. Byte Read-Modify-Write Cycle—32-Bit Port (TAS Instruction) MOTOROLA M68020 USER’S MANUAL 5- 41...
Page 90 State 0 MC68020—The processor asserts ECS and OCS in S0 to indicate the beginning of an external operand cycle. The processor also asserts RMC in S0 to identify a read- modify-write cycle. The processor places a valid address on A31–A0 and valid function codes on FC2–FC0.
Page 91 State 5 MC68020—The processor negates AS, DS, and DBEN during S5. If more than one read cycle is required to read in the operand(s), S0–S5 are repeated for each read cycle. When the read cycle(s) are complete, the processor holds the address, R/W , and FC2–FC0 valid in preparation for the write portion of the cycle.
Page 92 The CPU space type is encoded on A19–A16 during a CPU space operation and indicates the function that the processor is performing. On the MC68020/EC020, four of the encodings are implemented as shown in Figure 5-31. All unused values are reserved by Motorola for future use.
Page 93 Refer to Section 6 Exception Processing for details on the recognition of interrupts. The MC68020/EC020 takes an interrupt exception for a pending interrupt within one instruction boundary (after processing any other pending exception with a higher priority). The following paragraphs describe the various kinds of interrupt acknowledge bus cycles that can be executed as part of interrupt exception processing.
Page 94 IPL1, and IPL0, respectively). 3. The CPU space type field (A19–A16) is set to 1111, the interrupt acknowledge code. 4. Other address signals (A31–A20, A15–A4, and A0 for the MC68020; A23–A20, A15–A4, and A0 for the MC68EC020) are set to one.
Page 95 VECTOR # FROM 16-BIT PORT D7–D0 VECTOR # FROM 32-BIT PORT IPL2–IPL0 IPEND INTERRUPT READ CYCLE WRITE STACK ACKNOWLEDGE For the MC68EC020, A23–A4. This signal does not apply to the MC68EC020. Figure 5-33. Interrupt Acknowledge Cycle Timing MOTOROLA M68020 USER’S MANUAL 5- 47...
Page 96 When AVEC is asserted instead of DSACK1/DSACK0 during an interrupt acknowledge cycle, the MC68020/EC020 ignores the state of the data bus and internally generates the vector number, the sum of the interrupt level plus 24 ($18). Seven distinct autovectors, which correspond to the seven levels of interrupt available with IPL2–...
Page 97 INTERRUPT LEVEL FC2–FC0 SIZ1 SIZ0 DSACK1 DSACK0 DBEN D31–D0 IPL2–IPL0 AVEC INTERRUPT WRITE STACK READ CYCLE ACKNOWLEDGE AUTOVECTORED For the MC68EC020, A23–A4. This signal does not apply to the MC68EC020. Figure 5-34. Autovector Operation Timing MOTOROLA M68020 USER’S MANUAL 5- 49...
Page 98 1) NEGATE AS AND DS 2) GO TO B 1) PLACE LATCHED DATA IN INSTRUCTION SLAVE NEGATES DSACK1/DSACK0 OR BERR PIPELINE 2) CONTINUE PROCESSING 1) INITIATE ILLEGAL INSTRUCTION PROCESSING Figure 5-35. Breakpoint Acknowledge Cycle Flowchart 5-50 M68020 USER’S MANUAL MOTOROLA...
Page 99 BREAKPOINT ENCODING A15–A2 BREAKPOINT NUMBER A1–A0 FC2–FC0 WORD SIZ1 SIZ0 DSACK1 DSACK0 DBEN D23–D16 D15–D8 D7–D0 BERR HALT FETCHED BREAKPOINT READ CYCLE INSTRUCTION ACKNOWLEDGE EXECUTION INSTRUCTION WORD FETCH Figure 5-36. Breakpoint Acknowledge Cycle Timing MOTOROLA M68020 USER’S MANUAL 5- 51...
Page 100 SIZ1–SIZ0 DSACK1 DSACK0 DBEN D31–D0 BERR HALT INTERNAL READ WITH BERR ASSERTED STACK WRITE PROCESSING For the MC68EC020, A23–A0. This signal does not apply to the MC68EC020. Figure 5-37. Breakpoint Acknowledge Cycle Timing (Exception Signaled) 5-52 M68020 USER’S MANUAL MOTOROLA...
Page 101 (CpID), and A5–A0 specify the coprocessor interface register to be accessed. The memory management unit of an MC68020/EC020 system is always identified by a CpID of zero and has an extended register select field (A7–A0) in CPU space 0001 for use by the CALLM and RTM access level checking mechanism.
Page 102 (e.g., S2, S4, etc.) A—Signal is asserted in this bus state N—Signal is not asserted and/or remains negated in this bus state X—Don’t care S—Signal was asserted in previous state and remains asserted in this state 5-54 M68020 USER’S MANUAL MOTOROLA...
Page 103 When BERR is issued to terminate a bus cycle, the MC68020/EC020 may enter exception processing immediately following the bus cycle, or it may defer processing the exception.
Page 104 The processor terminates the bus cycle, negates the control signals (AS, DS, R/W, SIZ1, SIZ0, RMC, and, for the MC68020 only, ECS and OCS), and does not begin another bus cycle until the BERR and HALT signals have been negated by external logic. After a synchronization delay, the processor retries the previous cycle using the same access information (address, function code, size, etc.) The BERR signal should be negated before...
Page 105 DBEN D31–D24 D23–D16 D15–D8 D7–D0 BERR HALT BREAKPOINT EXCEPTION ACKNOWLEDGE READ CYCLE STACKING BUS ERROR FETCH For the MC68EC020, A23–A20. This signal does not apply to the MC68EC020. DSACK1/DSACK0 Figure 5-38. Bus Error without MOTOROLA M68020 USER’S MANUAL 5- 57...
Page 106 SIZ1–SIZ0 DSACK1 DSACK0 DBEN D31–D0 IPL2–IPL0 BERR HALT INTERNAL WRITE WITH BERR ASSERTED STACK WRITE PROCESSING For the MC68EC020, A23–A0. This signal does not apply to the MC68EC020. DSACK1/DSACK0 Figure 5-39. Late Bus Error with 5-58 M68020 USER’S MANUAL MOTOROLA...
Page 107 FC2–FC0 SIZ1–SIZ0 DSACK1 DSACK0 DATA BUS NOT DRIVEN D31–D0 BERR HALT WRITE CYCLE RETRY SIGNALED HALT RETRY CYCLE For the MC68EC020, A23–A0. This signal does not apply to the MC68EC020. Figure 5-40. Late Retry MOTOROLA M68020 USER’S MANUAL 5- 59...
Page 108 (A31–A0, FC2–FC0, SIZ1, SIZ0, R/W, AS, DS, and, for the MC68020 only, ECS and OCS) are also placed in the high-impedance state. Once bus mastership is returned to the MC68020/EC020, if HALT is still asserted, A31–A0 for the MC68020 or A23–A0 for the MC68EC020, FC2–FC0, SIZ1, SIZ0, and R/W are again...
Page 109 DSACK1 DSACK0 DBEN D31–D0 BERR HALT HALT READ READ (BUS ARBITRATION PERMITTED WHILE THE PROCESSOR IS HALTED) For the MC68EC020, A23–A0. This signal does not apply to the MC68EC020. Figure 5-41. Halt Operation Timing MOTOROLA M68020 USER’S MANUAL 5- 61...
Page 110 NOP instruction for this purpose is not required by most systems. 5.7 BUS ARBITRATION The bus design of the MC68020/EC020 provides for a single bus master at any one time: either the processor or an external device. One or more of the external devices on the bus can have the capability of becoming bus master.
Page 111 • BGACK must be inactive, indicating that no other bus master has claimed ownership of the bus. Figure 5-42 is a flowchart of MC68020 bus arbitration for a single device. Figure 5-43 is a timing diagram for the same operation. This technique allows processing of bus requests during data transfer cycles.
Page 112 PROCESSOR OPERATION 1) NEGATE BGACK Figure 5-42. MC68020 Bus Arbitration Flowchart for Single Request The timing diagram (see Figure 5-43) shows that BR is negated at the time that BGACK is asserted. This type of operation applies to a system consisting of the processor and one device capable of bus mastership.
Page 113 A31–A0 FC2–FC0 SIZ1–SIZ0 DSACK1 DSACK0 DBEN D31–D0 BGACK PROCESSOR DMA DEVICE PROCESSOR Figure 5-43. MC68020 Bus Arbitration Operation Timing for Single Request MOTOROLA M68020 USER’S MANUAL 5- 65...
Page 114 5.7.1.2 BUS GRANT (MC68020). The processor asserts BG as soon as possible after receipt of the bus request. BG assertion immediately follows internal synchronization except during a read-modify-write cycle or follows an internal decision to execute a bus cycle.
Page 115 5.7.1.4 BUS ARBITRATION CONTROL (MC68020). The bus arbitration control unit in the MC68020 is implemented with a finite state machine. As discussed previously, all asynchronous inputs to the MC68020 are internally synchronized in a maximum of two cycles of the processor clock.
Page 116 R and A. The MC68020 does not allow arbitration of the external bus during the read-modify-write sequence. For the duration of this sequence, the MC68020 ignores the BR input. If mastership of the MC68020 bus is required during a read-modify-write operation, BERR must be used to abort the read-modify-write sequence.
Page 117 A31–A0 FC2–FC0 SIZ1–SIZ0 DSACK1 DSACK0 DBEN D31–D0 BGACK BUS INACTIVE (ARBITRATION PERMITTED ALTERNATE MASTER PROCESSOR PROCESSOR WHILE THE PROCESSOR IS INACTIVE OR HALTED) Figure 5-45. MC68020 Bus Arbitration Operation Timing—Bus Inactive MOTOROLA M68020 USER’S MANUAL 5- 69...
Page 118 B R; it is usually asserted as soon as BR has been synchronized and recognized, except when the MC68020 has made an internal decision to execute a bus cycle. Then, the assertion of BG is deferred until the bus cycle has begun. Additionally, BG is not asserted until the end of a read-modify-write operation (when RMC is negated) in response to a BR signal.
Page 119 BG is deferred until the bus cycle has begun. BG may be routed through a daisy-chained network or through a specific priority-encoded network. The processor allows any type of external arbitration that follows the protocol. MOTOROLA M68020 USER’S MANUAL 5- 71...
Page 120 A23–A0 FC2–FC0 SIZ1–SIZ0 DSACK1 DSACK0 D31–D0 PROCESSOR DMA DEVICE PROCESSOR Figure 5-47. MC68EC020 Bus Arbitration Operation Timing for Single Request 5-72 M68020 USER’S MANUAL MOTOROLA...
Page 121 STATE 0 STATE 4 STATE1 STATE 3 STATE 2 STATE 5 STATE 6 R—BUS REQUEST G—BUS GRANT T —THREE-STATE CONTROL TO BUS CONTROL LOGIC X—DON'T CARE Figure 5-48. MC68EC020 Bus Arbitration State Diagram MOTOROLA M68020 USER’S MANUAL 5- 73...
Page 122 If mastership of the MC68EC020 bus is required during a read-modify-write operation, BERR must be used to abort the read-modify-write sequence. The bus arbitration sequence while the bus is inactive (i.e., executing internal operations such as a multiply instruction) is shown in Figure 5-49. 5-74 M68020 USER’S MANUAL MOTOROLA...
Page 123 BGACK and the negation of BR by the alternate bus master. Figure 5-50 assumes the alternate bus master does not assume bus mastership until the MC68EC020 AS is negated and MC68EC020 BG is asserted. MOTOROLA M68020 USER’S MANUAL 5- 75...
Page 124 RESET should be asserted for at least 520 clock periods to ensure that the processor resets. Asserting RESET for 10 clock periods is sufficient for resetting the processor logic; the additional clock periods prevent a RESET instruction from overlapping the external RESET signal. 5-76 M68020 USER’S MANUAL MOTOROLA...
Page 125 RESET instruction must extend beyond the reset period of the instruction by at least eight clock cycles to reset the processor. Figure 5-52 shows the timing information for the RESET instruction. MOTOROLA M68020 USER’S MANUAL 5- 77...
Page 126 A31–A0 FC2–FC0 SIZ1–SIZ0 DSACK1 DSACK0 DBEN D31–D0 HALT RESET RESET INTERNAL RESUME NORMAL READ 512 CLOCKS OPERATION For the MC68EC020, A23–A0. This signal does not apply to the MC68EC020. Figure 5-52. RESET Instruction Timing 5-78 M68020 USER’S MANUAL MOTOROLA...
Page 127 An introduction to exception processing, as one of the processing states of the MC68020/EC020, is given in Section 2 Processing States. This section describes exception processing in detail, describing the processing for each type of exception.
Page 128 6-1 contains a description of all the exception vector offsets defined for the MC68020/EC020. As shown in Table 6-1, the first 64 vectors are defined by Motorola, and 192 vectors are reserved for interrupt vectors defined by the user. However, external devices may use vectors reserved for internal purposes at the discretion of the system designer.
Page 129 FPCP Underflow FPCP Operand Error FPCP Overflow FPCP Signaling NAN Unassigned, Reserved PMMU Configuration PMMU Illegal Operation PMMU Access Level Violation 59–63 Unassigned, Reserved 64–255 User-Defined Vectors (192) SP—Supervisor Program Space SD—Supervisor Data Space MOTOROLA M68020 USER’S MANUAL 6- 3...
Page 130 HALT signal to indicate the halted condition. Execution of the RESET instruction does not cause a reset exception, nor does it affect any internal registers, but it does cause the MC68020/EC020 to assert the RESET signal, resetting all external devices.
Page 131 SR on the active supervisor stack. The saved PC value is the logical address of the instruction that was executing at the time the fault was detected. This is not necessarily the instruction that initiated the bus cycle since the processor overlaps MOTOROLA M68020 USER’S MANUAL 6- 5...
Page 132 The information saved on the stack is sufficient to identify the cause of the bus fault and recover from the error. For efficiency, the MC68020/EC020 uses two different bus error stack frame formats. When the bus error exception is taken at an instruction boundary, less information is required to recover from the error, and the processor builds the short bus fault stack frame as shown in Table 6-5.
Page 133 An illegal instruction is an instruction that contains any bit pattern in its first word that does not correspond to the bit pattern of the first word of a valid MC68020/EC020 instruction or a MOVEC instruction with an undefined register specification field in the first extension word.
Page 134 The saved value of the PC is the logical address of the first word of the instruction that caused the privilege violation. Instruction execution resumes after the required prefetches from the address in the privilege violation exception vector. M68020 USER’S MANUAL MOTOROLA...
Page 135 6.1.7 Trace Exception To aid in program development, the M68000 processors include an instruction-by- instruction tracing capability. The MC68020/EC020 can be programmed to trace all instructions or only instructions that change program flow. In the trace mode, an instruction generates a trace exception after it completes execution, allowing a debugger program to monitor execution of a program.
Page 136 The cpRESTORE instruction passes the format word of the coprocessor state frame to the coprocessor for validation. If the coprocessor does not recognize the format value, it signals the MC68020/EC020 to take a format error exception. Refer to Section 7 Coprocessor Interface Description for details of coprocessor-related exceptions.
Page 137 6.1.9 Interrupt Exceptions When a peripheral device requires the services of the MC68020/EC020 or is ready to send information that the processor requires, it may signal the processor to take an interrupt exception. The interrupt exception transfers control to a routine that responds appropriately.
Page 138 6 and one for level 7. When the MC68020/EC020 processes a level 6 interrupt, the interrupt priority mask is automatically updated with a value of 6 before entering the handler routine so that subsequent level 6 interrupts are masked.
Page 139 3 and then raised back to level 6, and a second MOTOROLA M68020 USER’S MANUAL 6- 13...
Page 140 6 interrupt is not processed. However, if the MC68020/EC020 is handling a level 7 interrupt (I2–I0 in the SR set to 111) and the external request is lowered to level 3 and then raised back to level 7, a second level 7 interrupt is processed. The second level 7 interrupt is processed because the level 7 interrupt is transition sensitive.
Page 141 The MC68020 asserts IPEND (note that IPEND is not implemented in the MC68EC020) when it makes an interrupt request pending. Figure 6-4 shows the assertion of IPEND relative to the assertion of an interrupt level on IPL2 – IPL0 . IPEND signals to external devices that an interrupt exception will be taken at an upcoming instruction boundary (following any higher priority exception).
Page 142 PREFETCH 3 WORDS BEGIN EXECUTION OF THE INTERRUPT END OF EXCEPTION PROCESSING HANDLER ROUTINE OR PROCESS A FOR THE INTERRUPT HIGHER PRIORITY EXCEPTION Does not apply to the MC68EC020. Figure 6-5. Interrupt Exception Processing Flowchart 6-16 M68020 USER’S MANUAL MOTOROLA...
Page 143 For the MC68020, if no higher priority interrupt has been synchronized, the IPEND signal is negated during state 0 (S0) of an interrupt acknowledge cycle, and the IPL2–IPL0 signals for the interrupt being acknowledged can be negated at this time. For the MC68EC020, if no higher priority interrupt has been synchronized, the IPL2–IPL0 signals...
Page 144 6.1.10 Breakpoint Instruction Exception To use the MC68020/EC020 in a hardware emulator, it must provide a means of inserting breakpoints in the emulator code and of performing appropriate operations at each breakpoint. For the MC68000 and MC68008, this can be done by inserting an illegal instruction at the breakpoint and detecting the illegal instruction exception from its vector location.
Page 145 Exception processing begins before instruction is Line F, Privilege Violation, cp Preinstruction executed. 4.0—cp Postinstruction Exception processing begins when current instruction 4.1—Trace or previous exception processing has completed. 4.2—Interrupt NOTE: 0.0 is the highest priority; 4.2 is the lowest. MOTOROLA M68020 USER’S MANUAL 6- 19...
Page 146 6.1.12 Return from Exception After the MC68020/EC020 has completed exception processing for all pending exceptions, it resumes normal instruction execution at the address in the vector for the last exception processed. Once the exception handler has completed execution, the processor must return to the system context prior to the exception (if possible).
Page 147 Otherwise, the processor reads the entire frame into the proper internal registers, deallocates the stack, and resumes normal processing. Once the processor begins to load the frame to restore its internal state, the assertion of the BERR signal MOTOROLA M68020 USER’S MANUAL 6- 21...
Page 148 SSW applies to data cycles only. Data and instruction stream faults may be pending simultaneously; the fault handler should be able to recognize any combination of the FC, FB, RC, RB, and DF bits. 6-22 M68020 USER’S MANUAL MOTOROLA...
Page 149 B. The address space for the bus cycle is the program space for the privilege level indicated in the copy of the SR on the stack. If the RB bit is clear, the words on the MOTOROLA M68020 USER’S MANUAL...
Page 150 1 = Rerun faulted bus cycle or run pending prefetch 0 = Do not rerun bus cycle Bits 11–9—Reserved by Motorola DF—Fault/Rerun Flag If the DF bit is set, a data fault has occurred and caused the exception. If the DF bit is set when the processor reads the stack frame, it reruns the faulted data access;...
Page 151 The fault occurs again unless the cause of the fault, such as a nonresident page in a virtual memory system, has been corrected. If the RB or RC bit is set and the MOTOROLA M68020 USER’S MANUAL 6- 25...
Page 152 When the MC68020/EC020 writes or reads a stack frame, it uses long-word operand transfers wherever possible. Using a long-word-aligned stack pointer with memory that is on a 32-bit port greatly enhances exception processing performance.
Page 153 During Coprocessor +$08 INSTRUCTION ADDRESS that caused the exception Instruction +$0C (supported with 'null INTERNAL REGISTERS, come again with 4 WORDS +$12 interrupts allowed' primitive) COPROCESSOR MIDINSTRUCTION STACK FRAME (10 WORDS) — FORMAT $9 MOTOROLA M68020 USER’S MANUAL 6- 27...
Page 154 INTERNAL REGISTERS, 2 WORDS +$2A +$2C DATA INPUT BUFFER +$30 INTERNAL REGISTERS, 3 WORDS +$36 +$38 VERSION # INTERNAL INFORMATION INTERNAL REGISTERS, 18 WORDS +$5A LONG BUS FAULT STACK FRAME (46 WORDS) — FORMAT $B 6-28 M68020 USER’S MANUAL MOTOROLA...
Page 155 This section is intended for designers who are implementing coprocessors to interface with the MC68020/EC020. The designer of a system that uses one or more Motorola coprocessors (the MC68881 or MC68882 floating-point coprocessor, for example) does not require a detailed knowledge of the M68000 coprocessor interface.
Page 156 The communication protocol defined for the M68000 coprocessor interface is described in 7.2 Coprocessor Instruction Types. The algorithms that implement the M68000 coprocessor interface are provided in the microcode of the MC68020/EC020 and are completely transparent to the MC68020/EC020 programming model. For example, floating-point operations are not implemented in the MC68020/EC020 hardware.
Page 157 (CpID) field. The MC68020/EC020 uses the CpID field to indicate the coprocessor to which the instruction applies. F-line operation words, in which the CpID is zero, are not coprocessor instructions for the MC68020/EC020. Instructions with a CpID of zero and a nonzero type field are unimplemented instructions that cause the MOTOROLA M68020 USER’S MANUAL...
Page 158 CpID equal to zero (except via the MOVES instruction). CpID codes of 000–101 are reserved for current and future Motorola coprocessors, and CpID codes of 110–111 are reserved for user-defined coprocessors. The Motorola CpID code of 001 designates the MC68881 or MC68882 floating-point coprocessor.
Page 159 Figure 7-2. Asynchronous Non-DMA M68000 Coprocessor Interface Signal Usage The MC68020/EC020 accesses the registers in the CIR set using standard asynchronous bus cycles. Thus, the bus interface implemented by a coprocessor for its interface register set must satisfy the MC68020/EC020 address, data, and control signal timing. The MC68020/EC020 bus operation is described in detail in Section 5 Bus Operation.
Page 160 The FC2–FC0 and A19–A16 signals indicate a coprocessor access; A15–A13 indicate which of the possible eight coprocessors (000–111) is being accessed. Bits A31–A20 and A12–A5 of the MC68020 address bus and bits A23–A20 and A12–A5 of the MC68EC020 address bus are always zero during a coprocessor access.
Page 161 The category name indicates the type of operations provided by the coprocessor instructions in the category. The instruction category also determines the CIR accessed by the MC68020/EC020 to initiate instruction and communication protocols between the main processor and the coprocessor necessary for instruction execution.
Page 162 Programmer’s Reference Manual ). During the execution of a cpGEN instruction, the coprocessor can use a coprocessor response primitive to request that the MC68020/EC020 perform an effective address calculation necessary for that instruction. Using the effective address specifier field of the F-line operation code, the processor then determines the effective addressing mode.
Page 163 The main processor can then execute the next instruction in the instruction stream. However, if a trace exception is pending, the MC68020/EC020 does not terminate communication with the coprocessor until the coprocessor indicates that it has completed all processing associated with the cpGEN instruction (refer to 7.5.2.5 Trace Exceptions).
Page 164 NOTES: 1. "Come Again" indicates that further service of the main processor is being requested by the coprocessor. 2. The next instruction should be the operation word pointed to by the ScanPC at this point. The operation of the MC68020/EC020 ScanPC is discussed in 7.4.1 ScanPC.
Page 165 "Come Again" when used during the execution of a conditional category instruction. If a "Come Again" attribute is not indicated in one of these primitives, the main processor will initiate protocol violation exception processing (see 7.5.2.1 Protocol Violations). Figure 7-8. Coprocessor Interface Protocol for Conditional Category Instructions MOTOROLA M68020 USER’S MANUAL 7- 11...
Page 166 Bits 5–0 of the F-line operation word contain the coprocessor condition selector field. The MC68020/EC020 writes the entire operation word to the condition CIR to initiate execution of the branch instruction by the coprocessor.
Page 167 CIR to determine its next action. The coprocessor can MOTOROLA M68020 USER’S MANUAL 7- 13...
Page 168 The second word of the cpScc instruction format contains the coprocessor condition selector field in bits 5–0. Bits 15–6 of this word are reserved by Motorola and should be zero to ensure compatibility with future M68000 products. This word is written to the condition CIR to initiate execution of the cpScc instruction.
Page 169 The second word of the cpDBcc instruction format contains the coprocessor condition selector field in bits 5–0 and should contain zeros in bits 15–6 (reserved by Motorola) to maintain compatibility with future M68000 products. This word is written to the condition CIR to initiate execution of the cpDBcc instruction.
Page 170 (–1) after being decremented, the main processor branches to the destination address to continue instruction execution. The MC68020/EC020 adds the displacement to the scanPC (refer to 7.4.1 ScanPC) to determine the address of the next instruction. The scanPC must point to the 16-bit displacement in the instruction stream when the destination address is calculated.
Page 171 The second word of the cpTRAPcc instruction format contains the coprocessor condition selector in bits 5–0 and should contain zeros in bits 15–6 (these bits are reserved by Motorola) to maintain compatibility with future M68000 products. This word is written to the condition CIR to initiate execution of the cpTRAPcc instruction.
Page 172 Figure 7-14 shows the format of a coprocessor state frame. The format and length fields of the coprocessor state frame format comprise the format word. During execution of the cpSAVE instruction, the MC68020/EC020 calculates the state frame effective address from information in the operation word of the instruction and stores a format word at this effective address.
Page 173 The MC68020/EC020 interprets the reserved format codes ($03–$0F) as invalid format words. The lower byte of the coprocessor format word specifies the size in bytes (which must be a multiple of four) of the coprocessor state frame.
Page 174 In this situation, the coprocessor can return the invalid format word when the main processor reads the save CIR to initiate the cpSAVE instruction while either another cpSAVE or cpRESTORE instruction is executing. If the 7-20 M68020 USER’S MANUAL MOTOROLA...
Page 175 Figure 7-15. Coprocessor Context Save Instruction Format (cpSAVE) The control alterable and predecrement addressing modes are valid for the cpSAVE instruction. Other addressing modes cause the MC68020/EC020 to initiate F-line emulator exception processing as described in 7.5.2.2 F-Line Emulator Exceptions.
Page 176 MC68020/EC020 initiates format error exception processing (refer to 7.5.1.5 Format Errors). The coprocessor and main processor coordinate the transfer of the internal state of the coprocessor using the operand CIR. The MC68020/EC020 completes the coprocessor context save by repeatedly reading the operand CIR and writing the 7-22 M68020 USER’S MANUAL...
Page 177 Following a cpSAVE instruction, the coprocessor should be in an idle state—that is, not executing any coprocessor instructions. The cpSAVE instruction is a privileged instruction. When the MC68020/EC020 identifies a cpSAVE instruction, it checks the S-bit in the SR to determine whether it is operating at the supervisor privilege level.
Page 178 PROCEED WITH EXECUTION OF NEXT INSTRUCTION NOTES: 1. See 7.6.1.5 Format Error. 2. The MC68020/EC020 uses the length field in the format word read during M2 to determine the number of bytes to read from memory and write to the operand CIR.
Page 179 (refer to 7.5.1.5 Format Errors). The cpRESTORE instruction is a privileged instruction. When the MC68020/EC020 accesses a cpRESTORE instruction, it checks the S-bit in the SR. If the MC68020/EC020 attempts to execute a cpRESTORE instruction while at the user privilege level (S-bit in the SR is clear), it initiates privilege violation exception processing without accessing any of the CIRs (refer to 7.5.2.3 Privilege Violations).
Page 180 (XA) in the control CIR. The MC68020/EC020 sets the abort bit (AB) in the control CIR to abort any coprocessor instruction in progress. (The 14 most significant bits of both masks are undefined.) The MC68020/EC020 aborts a coprocessor instruction when it...
Page 181 5–0 of the 16-bit condition CIR. Bits 15–6 are undefined and reserved by Motorola. The offset from the base address of the CIR set for the condition CIR is $0E. Figure 7-20 shows the format of the condition CIR.
Page 182 General Format, consist of detailed descriptions of the M68000 coprocessor response primitives supported by the MC68020/EC020. Any response primitive that the MC68020/EC020 does not recognize causes it to initiate protocol violation exception processing (refer to 7.5.2.1 Protocol Violations). This processing of undefined primitives supports emulation of extensions to the M68000 coprocessor response primitive set by the protocol violation exception handler.
Page 183 During the execution of conditional category instructions, when the coprocessor terminates the instruction protocol, the MC68020/EC020 assumes that the scanPC is pointing to the word following the last of any coprocessor-defined extension words in the instruction format.
Page 184 (main processor read). If the operation indicated by a given response primitive does not involve an explicit operand transfer, the value of this bit depends on the particular primitive encoding. 7-30 M68020 USER’S MANUAL MOTOROLA...
Page 185 The MC68020/EC020 responds to the busy primitive differently in a special case that can occur during a breakpoint operation (refer to Section 6 Exception Processing). This...
Page 186 The TF bit is only relevant for null primitives with CA = 0 that are used by the coprocessor during the execution of a conditional instruction. The MC68020/EC020 processes a null primitive with CA = 1 in the same manner whether executing a general or conditional category coprocessor instruction. If the coprocessor sets CA and IA in the null primitive, the main processor services pending interrupts using a midinstruction stack frame (refer to Figure 7-43) and reads the response CIR again.
Page 187 Coprocessor Instruction Completed; Main Processor Completes Instruction Service Pending Exceptions or Execute Execution Based on TF = c. Next Instruction x = Don't Care c = 1 or 0 Depending on Coprocessor Condition Evaluation MOTOROLA M68020 USER’S MANUAL 7- 33...
Page 188 When the MC68020/EC020 reads the supervisor check primitive from the response CIR, it checks the value of the S-bit in the SR. If S = 0 (main processor operating at user privilege level), the main processor aborts the coprocessor instruction by writing an abort mask to the control CIR (refer to 7.3.2 Control CIR).
Page 189 CIR. If the length field is not an even multiple of four bytes, the last two bytes from the instruction stream are transferred using a word write to the operand CIR. MOTOROLA M68020 USER’S MANUAL 7- 35...
Page 190 After the effective address is calculated, the resulting 32-bit value is written to the operand address CIR. The MC68020/EC020 only calculates effective addresses for control alterable addressing modes in response to this primitive. If the addressing mode in the operation word is not a control alterable mode, the main processor aborts the instruction by writing a $0001 to the control CIR and initiates F-line emulation exception processing (refer to 7.5.2.2 F-Line...
Page 191 Any Effective Address (No Restriction) Even when the valid EA fields specified in the primitive and in the instruction operation word match, the MC68020/EC020 initiates protocol violation exception processing if the primitive requests a write to an unalterable effective address.
Page 192 The MC68020/EC020 sign-extends a byte or word-sized operand to a long-word value when it is transferred to an address register (A7–A0) using this primitive with the register direct effective addressing mode.
Page 193 For example, if the previously evaluated effective address was PC relative and the MC68020/EC020 is at the user privilege level (S = 0 in SR), the MC68020/EC020 writes to user data space at the previously calculated program relative address (the 32-bit value in the temporary internal register of the processor).
Page 194 Transfer Data Primitive does not replace the effective address value that has been calculated by the MC68020/EC020. The address that the main processor obtains in response to the take address and transfer data primitive is not available to the write to previously evaluated effective address primitive.
Page 195 The transfer single main processor register primitive uses the CA, PC, and DR bits as described in 7.4.2 Coprocessor Response Primitive General Format. If the coprocessor issues this primitive with CA = 0 during a conditional category instruction, the main processor initiates protocol violation exception processing. MOTOROLA M68020 USER’S MANUAL 7- 41...
Page 196 CIR. This code determines which main processor control register is transferred. Table 7-5 lists the valid control register select codes. If the control register select code is not valid, the MC68020/EC020 initiates protocol violation exception processing (refer to 7.5.2.1 Protocol Violations).
Page 197 This primitive applies to general category instructions. If the coprocessor issues this primitive during the execution of a conditional category instruction, the main processor initiates protocol violation exception processing. Figure 7-37 shows the format of the transfer multiple coprocessor registers primitive. MOTOROLA M68020 USER’S MANUAL 7- 43...
Page 198 (DR = 1), the control alterable and predecrement addressing modes are valid. Invalid addressing modes cause the MC68020/EC020 to abort the instruction by writing an abort mask to the control CIR (refer to 7.3.2 Control CIR) and to initiate F-line emulator exception processing (refer to 7.5.2.2 F-Line Emulator Exceptions).
Page 199 7.4.17 Transfer Status Register and ScanPC Primitive The transfer status register and the scanPC primitive transfers values between the coprocessor and the MC68020/EC020 SR. On an optional basis, the scanPC also makes transfers. This primitive applies to general category instructions. If the coprocessor issues this primitive during the execution of a conditional category instruction, the main processor initiates protocol violation exception processing.
Page 200 S-bit of the SR. If the MC68020/EC020 is operating in the trace on change of flow mode (T1, T0 in the SR = 01) when the coprocessor instruction begins to execute and if this primitive is issued with DR = 1 (from coprocessor to main processor), the MC68020/EC020 prepares to take a trace exception.
Page 201 Section 6 Exception Processing. The vector number for the exception is taken from the vector number field of the primitive, and the MC68020/EC020 uses the four-word stack frame format shown in Figure 7-41. STATUS REGISTER PROGRAM COUNTER VECTOR NUMBER Figure 7-41.
Page 202 CIR. The MC68020/EC020 then performs exception processing as described in Section 6 Exception Processing. The vector number for the exception is taken from the vector number field of the primitive, and the MC68020/EC020 uses the 10-word stack frame format shown in Figure 7-43.
Page 203 7.3.2 Control CIR). The MC68020/EC020 then performs exception processing as described in Section 6 Exception Processing. The vector number for the exception is taken from the vector number field of the primitive, and the MC68020/EC020 uses the six- word stack frame format shown in Figure 7-45.
Page 204 When the MC68020/EC020 receives the take postinstruction exception primitive, it assumes that the coprocessor either completed or aborted the instruction with an exception. If the exception handler does not modify the stack frame, the MC68020/EC020 returns from the exception handler to begin execution at the location specified by the scanPC field of the stack frame.
Page 205 7.4.19 Take Midinstruction Exception Primitive. If the exception handler does not modify the stack frame, the MC68020/EC020 returns from the exception handler and reads the response CIR. MOTOROLA M68020 USER’S MANUAL...
Page 206 7.4.18 Take Preinstruction Exception Primitive. If the exception handler does not modify the main processor stack frame, an RTE instruction causes the MC68020/EC020 to reinitiate the instruction that took the exception. The coprocessor designer should ensure that the state of the coprocessor is not irrecoverably altered by an illegal command or condition exception if the system supports emulation of the unrecognized command or condition word.
Page 207 14. Thus, if the exception handler does not modify the stack frame, the MC68020/EC020 restarts the cpRESTORE instruction when the RTE instruction in the handler is executed. If the coprocessor returns the invalid format code when the main processor reads the save CIR to initiate a cpSAVE instruction, the main processor performs format error exception processing as outlined for the cpRESTORE instruction.
Page 208 Transfer Status and ScanPC Protocol: If Used with Conditional Instruction Other: 1. Trace—Trace Made Pending if MC68020/EC020 in “Trace on Change of Flow” Mode and DR = 1 2. Address Error—If Odd Value Written to ScanPC Take Preinstruction, Midinstruction, or Postinstruction Exception Exception Depends on Vector Supplies in Primitive Use of this primitive with CA = 0 will cause protocol violation on conditional instructions.
Page 209 If the main processor determines that an F-line operation word is not valid, it initiates F-line emulator exception processing. Any F-line operation word with bits 8–6 = 110 or 111 causes the MC68020/EC020 to initiate exception processing without initiating any communication with the coprocessor for that instruction.
Page 210 MC68020/EC020 takes a trace exception after completing each instruction. In the trace on change of flow mode, the MC68020/EC020 takes a trace exception after each instruction that alters the SR or places an address other than the address of the next instruction in the PC.
Page 211 If T1, T0 = 01 in the MC68020/EC020 SR (trace on change of flow mode) when a general category instruction is initiated, a trace exception is taken for the instruction only when the coprocessor issues a transfer status register and scanPC primitive with DR = 1 during the execution of that instruction.
Page 212 If the MC68020/EC020 reads a format word with an invalid length field from the save CIR during the cpSAVE instruction, it aborts the coprocessor instruction by writing an abort mask to the control CIR (refer to 7.3.2 Control CIR) and...
Page 213 The system designer can design a coprocessor to be reset and initialized by both reset types or by external reset signals only. To be consistent with the MC68020/EC020 design, the coprocessor should be affected by external reset signals only and not by RESET instructions, because the coprocessor is an extension to the main processor programming model and to the internal state of the MC68020/EC020.
Page 214 Busy Transfer Multiple Coprocessor Registers LENGTH Transfer Status Register and ScanPC Supervisor Check Take Address and Transfer Data LENGTH Transfer Multiple Main Processor Registers Transfer Operation Word Null Evaluate and Transfer Effective Address 7-60 M68020 USER’S MANUAL MOTOROLA...
Page 215 Transfer from Instruction Stream LENGTH Evaluate Effective Address and Transfer Data VALID EA LENGTH Take Preinstruction Exception VECTOR NUMBER Take Midinstruction Exception VECTOR NUMBER Take Postinstruction Exception VECTOR NUMBER Write to Previously Evaluated Effective Address LENGTH MOTOROLA M68020 USER’S MANUAL 7- 61...
Page 216 8.1.1 Instruction Cache and Prefetch The on-chip cache of the MC68020/EC020 is an instruction-only cache. Its purpose is to increase execution efficiency by providing a quick store for instructions. Instruction prefetches that hit in the cache will occur with no delay in instruction execution.
Page 217 (e.g., due to a branch to an odd-word location), the MC68020/EC020 will read the even word associated with the long-word base address at the same time as (32-bit memory) or before (8- or 16-bit memory) the odd word is read.
Page 218 MOVE to SR instruction to lower the interrupt mask level. Otherwise, the MOVE to SR instruction may complete before the write is accomplished, and a new interrupt exception will be generated for an old interrupt request. MOTOROLA M68020 USER’S MANUAL 8- 3...
Page 219 + 8 ADD #4 ••• Figure 8-3 shows processor activity on the first example instruction stream. It shows the activity of the external bus, the bus controller, the sequencer, and the attributed instruction execution time. M68020 USER’S MANUAL MOTOROLA...
Page 220 MOVE #3 is absorbed by the execution time of MOVE #3. This overlap shortens the effective execution time of ADD #4 by one clock, giving it an attributed execution time of one clock. MOTOROLA M68020 USER’S MANUAL 8- 5...
Page 221 Although the total execution time of the instruction segment does not change in this example, the individual instruction times are significantly different. This example demonstrates that the effects of overlap are not only instruction-sequence dependent but are also dependent upon the alignment of the instruction stream in memory. M68020 USER’S MANUAL MOTOROLA...
Page 222 Since prefetch occurs with no delay, the bus controller is idle more often. Example 4 Idle clock cycles, such as those shown in example 3, are useful in MC68020/EC020 systems that require wait states when accessing external memory. This fact is illustrated in example 4 (see Figure 8-6) with the following assumptions: 1.
Page 223 13 clocks. Examples 1–4 demonstrate the complexity of instruction timing calculation for the MC68020/EC020. It is impossible to anticipate individual instruction timing as an absolute number of clock cycles due to the dependency of overlap on the instruction sequence and alignment as well as the number of wait states in memory.
Page 224 8.2 INSTRUCTION TIMING TABLES The instruction times given in the following illustration include the following assumptions about the MC68020/EC020 system: 1. All operands are long-word aligned as is the stack, 2. The data bus is 32 bits, and 3. Memory access occurs with no wait states (three-cycle read/write).
Page 225 1.MULU.L (D7),D1:D2 #<data>.W,Dn MUL.L EA,Dn 2.BFCLR $6000{0:8} #<data>.W.,$XXX.W BFCLR Mem (<5 bytes) 3.DIVS.L #$10000,D3:D4 #<data>.W,#<data>.L DIVS.L EA, Dn Execution time = 2 + 43 + 5 + 16 + 6 + 90 = 102 clock periods 8-10 M68020 USER’S MANUAL MOTOROLA...
Page 226 BC, CC, or WC timing. Table 8-3. Observed Instruction Timings Example 1 Example 2 Example 3 Example 4 Instruction #1) MOVE.L D4,(A1)+ #2) ADD.L D4,D5 #3) MOVE.L (A1),–(A2) #4) ADD.L D5,D6 Total (16) (16) (12) (13) MOTOROLA M68020 USER’S MANUAL 8- 11...
Page 227 Although the timing tables cannot accurately predict the instruction timing that would be observed when executing an instruction stream on the MC68020/EC020, the tables can be used to calculate best-case and worst-case bounds for instruction timing. Absolute instruction timing must be measured by using the microprocessor itself to execute the target instruction stream.
Page 228 B = Base address; 0, An, PC, Xn, An + Xn. Form does not affect timing. = Index; 0, Xn NOTE: Xn cannot be in B and I at the same time. Scaling and size of Xn do not affect timing. MOTOROLA M68020 USER’S MANUAL 8- 13...
Page 229 #<data >.W,(d 32 ,B) 10(1/0/0) 15(1/0/0) 19(1/3/0) #<data >.L,(d 32 ,B) 11(1/0/0) 17(1/0/0) 21(1/3/0) #<data >.W,([B],I) 9(2/0/0) 14(2/0/0) 16(2/2/0) #<data >.L,([B],I) 10(2/0/0) 16(2/0/0) 18(2/2/0) #<data >.W,([B],I,d 16 ) 11(2/0/0) 16(2/0/0) 19(2/2/0) #<data >.L,([B],I,d 16 ) 12(2/0/0) 18(2/0/0) 21(2/2/0) 8-14 M68020 USER’S MANUAL MOTOROLA...
Page 230 B = Base address; 0, An, PC, Xn, An + Xn. Form does not affect timing. = Index; 0, Xn NOTE: Xn cannot be in B and I at the same time. Scaling and size of Xn do not affect timing. MOTOROLA M68020 USER’S MANUAL 8- 15...
Page 231 B = Base address; 0, An, PC, Xn, An + Xn. Form does not affect timing. = Index; 0, Xn NOTE: Xn cannot be in B and I at the same time. Scaling and size of Xn do not affect timing. 8-16 M68020 USER’S MANUAL MOTOROLA...
Page 232 #<data >.L,([B],I,d 11(1/0/0) 17(1/0/0) 20(1/2/0) #<data >.W,([B],I,d 10(1/0/0) 15(1/0/0) 19(1/2/0) #<data >.L,([d 16 ,B],I,d 11(1/0/0) 17(1/0/0) 21(1/3/0) #<data >.W,([d ,B],I) 10(1/0/0) 15(1/0/0) 18(1/2/0) #<data >.L,([d ,B],I) 11(1/0/0) 17(1/0/0) 20(1/2/0) #<data >.W,([d ,B],I,d 12(1/0/0) 17(1/0/0) 21(1/2/0) MOTOROLA M68020 USER’S MANUAL 8- 17...
Page 233 B = Base address; 0, An, PC, Xn, An + Xn. Form does not affect timing. = Index; 0, Xn NOTE: Xn cannot be in B and I at the same time. Scaling and size of Xn do not affect timing. 8-18 M68020 USER’S MANUAL MOTOROLA...
Page 234 B = Base address; 0, An, PC, Xn, An + Xn, PC + Xn. Form does not affect timing. = Index; 0, Xn NOTE: Xn cannot be in B and I at the same time. Scaling and size of Xn do not affect timing. MOTOROLA M68020 USER’S MANUAL 8- 19...
Page 235 13(2/0/0) 13(2/0/0) 16(2/0/1) 16(2/0/1) 16(2/0/1) 16(2/0/1) 16(2/0/1) 18(2/0/1) ,B],I) 15(2/0/0) 15(2/0/0) 18(2/0/1) 18(2/0/1) 18(2/0/1) 18(2/0/1) 18(2/0/1) 20(2/0/1) ,B],I,d 17(2/0/0) 17(2/0/0) 20(2/0/1) 20(2/0/1) 20(2/0/1) 20(2/0/1) 20(2/0/1) 22(2/0/1) ,B],I,d 17(2/0/0) 17(2/0/0) 20(2/0/1) 20(2/0/1) 20(2/0/1) 20(2/0/1) 20(2/0/1) 22(2/0/1) 8-20 M68020 USER’S MANUAL MOTOROLA...
Page 236 20(2/0/1) 21(2/0/1) 21(2/0/1) 25(2/0/1) 23(3/0/1) 25(3/0/1) 26(3/0/1) ,B],I) 20(2/0/1) 22(2/0/1) 23(2/0/1) 23(2/0/1) 27(2/0/1) 25(3/0/1) 27(3/0/1) 28(3/0/1) ,B],I,d 22(2/0/1) 24(2/0/1) 25(2/0/1) 25(2/0/1) 29(2/0/1) 27(3/0/1) 29(3/0/1) 30(3/0/1) ,B],I,d 22(2/0/1) 24(2/0/1) 25(2/0/1) 25(2/0/1) 29(2/0/1) 27(3/0/1) 29(3/0/1) 30(3/0/1) MOTOROLA M68020 USER’S MANUAL 8- 21...
Page 237 ,B],I,d 25(3/0/1) 27(3/0/1) 28(3/0/1) 29(3/0/1) 31(3/0/1) 32(3/0/1) ,B],I,d 25(3/0/1) 27(3/0/1) 28(3/0/1) 29(3/0/1) 31(3/0/1) 32(0/0/1) ,B],I) 27(3/0/1) 29(3/0/1) 30(3/0/1) 31(3/0/1) 33(3/0/1) 34(3/0/1) ,B],I,d 29(3/0/1) 31(3/0/1) 32(3/0/1) 33(3/0/1) 35(3/0/1) 36(3/0/1) ,B],I,d 29(3/0/1) 31(3/0/1) 32(3/0/1) 33(3/0/1) 35(3/0/1) 36(3/0/1) 8-22 M68020 USER’S MANUAL MOTOROLA...
Page 238 18(2/0/0) 19(2/0/1) 19(2/0/1) 19(2/0/1) 19(2/0/1) 19(2/0/1) 21(2/0/1) ,B],I) 20(2/0/0) 20(2/0/0) 21(2/0/1) 21(2/0/1) 21(2/0/1) 21(2/0/1) 21(2/0/1) 23(2/0/1) ,B],I,d 22(2/0/0) 22(2/0/0) 23(2/0/1) 23(2/0/1) 23(2/0/1) 23(2/0/1) 23(2/0/1) 25(2/0/1) ,B],I,d 22(2/0/0) 22(2/0/0) 23(2/0/1) 23(2/0/1) 23(2/0/1) 23(2/0/1) 23(2/0/1) 25(2/0/1) MOTOROLA M68020 USER’S MANUAL 8- 23...
Page 239 21(2/0/1) 23(2/0/1) 22(2/0/1) 24(2/0/1) 28(2/0/1) 26(3/0/1) 28(3/0/1) 29(3/0/1) ,B],I) 23(2/0/1) 25(2/0/1) 24(2/0/1) 26(2/0/1) 30(2/0/1) 28(3/0/1) 30(3/0/1) 31(3/0/1) ,B],I,d 25(2/0/1) 27(2/0/1) 26(2/0/1) 28(2/0/1) 32(2/0/1) 30(3/0/1) 32(3/0/1) 33(3/0/1) ,B],I,d 25(2/0/1) 27(2/0/1) 26(2/0/1) 28(2/0/1) 32(2/0/1) 30(3/0/1) 32(3/0/1) 33(3/0/1) 8-24 M68020 USER’S MANUAL MOTOROLA...
Page 240 28(3/0/1) 30(3/0/1) 31(3/0/1) 32(3/0/1) 34(3/0/1) 35(3/0/1) ,B],I,d 28(3/0/1) 30(3/0/1) 31(3/0/1) 32(3/0/1) 34(3/0/1) 35(3/0/1) ,B],I) 30(3/0/1) 32(3/0/1) 33(3/0/1) 34(3/0/1) 36(3/0/1) 37(3/0/1) ,B],I,d 32(3/0/1) 34(3/0/1) 35(3/0/1) 36(3/0/1) 38(3/0/1) 39(3/0/1) ,B],I,d 32(3/0/1) 34(3/0/1) 35(3/0/1) 36(3/0/1) 38(3/0/1) 39(3/0/1) MOTOROLA M68020 USER’S MANUAL 8- 25...
Page 241 23(2/3/0) 23(2/3/0) 25(2/3/1) 25(2/3/1) 25(2/3/1) 27(2/3/1) 27(2/3/1) 29(2/4/1) ,B],I) 23(2/3/0) 23(2/3/0) 25(2/3/1) 25(2/3/1) 25(2/3/1) 27(2/3/1) 27(2/3/1) 29(2/4/1) ,B],I,d 25(2/3/0) 25(2/3/0) 27(2/3/1) 27(2/3/1) 27(2/3/1) 29(2/3/1) 29(2/3/1) 31(2/4/1) ,B],I,d 27(2/4/0) 27(2/4/0) 29(2/4/1) 29(2/4/1) 29(2/4/1) 31(2/4/1) 31(2/4/1) 33(2/5/1) 8-26 M68020 USER’S MANUAL MOTOROLA...
Page 242 30(2/4/1) 28(2/3/1) 32(2/4/1) 37(2/4/1) 28(3/3/1) 35(3/4/1) 38(3/4/1) ,B],I) 27(2/3/1) 30(2/4/1) 28(2/3/1) 32(2/4/1) 37(2/4/1) 28(3/3/1) 35(3/4/1) 38(3/4/1) ,B],I,d 29(2/3/1) 32(2/4/1) 30(2/3/1) 34(2/4/1) 39(2/4/1) 30(3/3/1) 37(3/4/1) 40(3/4/1) ,B],I,d 31(2/4/1) 34(2/5/1) 32(2/4/1) 36(2/5/1) 41(2/5/1) 32(3/4/1) 39(3/5/1) 42(3/5/1) MOTOROLA M68020 USER’S MANUAL 8- 27...
Page 243 ,B],I,d 34(3/4/1) 37(3/4/1) 40(3/5/1) 41(3/4/1) 42(3/5/1) 44(3/5/1) ,B],I,d 35(3/4/1) 38(3/4/1) 41(3/5/1) 42(3/4/1) 43(3/5/1) 45(3/5/1) ,B],I) 35(3/4/1) 38(3/4/1) 41(3/5/1) 42(3/4/1) 43(3/5/1) 45(3/5/1) ,B],I,d 37(3/4/1) 40(3/4/1) 43(3/5/1) 44(3/4/1) 45(3/5/1) 47(3/5/1) ,B],I,d 39(3/5/1) 42(3/5/1) 45(3/6/1) 46(3/5/1) 47(3/6/1) 49(3/6/1) 8-28 M68020 USER’S MANUAL MOTOROLA...
Page 244 5(0/0/1) 5(0/0/1) 7(0/1/1) MOVE 0(0/0/0) 2(0/0/0) 3(0/1/0) SWAP Rx,Ry 1(0/0/0) 4(0/0/0) 4(0/1/0) n—Number of Registers to Transfer RL—Register List Add Fetch Effective Address Time †Add Calculate Effective Address Time ‡Add Calculate Immediate Address Time MOTOROLA M68020 USER’S MANUAL 8- 29...
Page 245 MUL.L EA,Dn 41(0/0/0) 43(0/0/0) 44(0/1/0) DIVU.W EA,Dn 42(0/0/0) 44(0/0/0) 44(0/1/0) DIVU.L EA,Dn 76(0/0/0) 78(0/0/0) 79(0/1/0) DIVS.W EA,Dn 54(0/0/0) 56(0/0/0) 57(0/1/0) DIVS.L EA,Dn 88(0/0/0) 90(0/0/0) 91(0/1/0) Add Fetch Effective Address Time Add Fetch Immediate Address Time 8-30 M68020 USER’S MANUAL MOTOROLA...
Page 246 3(0/1/0) #<data >,Mem 3(0/0/1) 4(0/0/1) 6(0/1/1) SUBI #<data >,Dn 0(0/0/0) 2(0/0/0) 3(0/1/0) SUBI #<data >,Mem 3(0/0/1) 4(0/0/1) 6(0/1/1) CMPI #<data >,EA 0(0/0/0) 2(0/0/0) 3(0/1/0) Add Fetch Effective Address Time Add Fetch Immediate Address Time MOTOROLA M68020 USER’S MANUAL 8- 31...
Page 247 3(0/1/0) SUBX –(An),–(An) 10(2/0/1) 12(2/0/1) 13(2/1/1) CMPM (An)+,(An)+ 8(2/0/0) 9(2/0/0) 10(2/1/0) PACK Dn,Dn,#<data > 3(0/0/0) 6(0/0/0) 7(0/1/0) PACK –(An),–(An),#<data > 11(1/0/1) 13(1/0/1) 13(1/1/1) UNPK Dn,Dn,#<data > 5(0/0/0) 8(0/0/0) 9(0/1/0) UNPK –(An),–(An),#<data > 11(1/0/1) 13(1/0/1) 13(1/1/1) 8-32 M68020 USER’S MANUAL MOTOROLA...
Page 248 1(0/0/0) 4(0/0/0) 4(0/1/0) NBCD 6(0/0/0) 6(0/0/0) 6(0/1/0) 1(0/0/0) 4(0/0/0) 4(0/1/0) † 6(0/0/1) 6(0/0/1) 6(0/1/1) 1(0/0/0) 4(0/0/0) 4(0/1/0) † 12(1/0/1) 12(1/0/1) 13(1/1/1) 0(0/0/0) 2(0/0/0) 3(0/1/0) Add Fetch Effective Address Time †Add Calculate Effective Address Time MOTOROLA M68020 USER’S MANUAL 8- 33...
Page 249 7(0/0/1) 7(0/0/1) 7(0/1/1) Mem by 1 7(0/0/1) 7(0/0/1) 7(0/1/1) ROXL 9(0/0/0) 12(0/0/0) 12(0/1/0) ROXR 9(0/0/0) 12(0/0/0) 12(0/1/0) ROXd Mem by 1 5(0/0/1) 5(0/0/1) 6(0/1/1) Add Fetch Effective Address Time d—Direction of Shift/Rotate, L or R 8-34 M68020 USER’S MANUAL MOTOROLA...
Page 250 4(0/0/1) 5(0/1/1) BSET #<data >,Dn 1(0/0/0) 4(0/0/0) 5(0/1/0) BSET Dn,Dn 1(0/0/0) 4(0/0/0) 5(0/1/0) BSET #<data >,Mem 4(0/0/1) 4(0/0/1) 5(0/1/1) BSET Dn,Mem 4(0/0/1) 4(0/0/1) 5(0/1/1) Add Fetch Effective Address Time Add Fetch Immediate Address Time MOTOROLA M68020 USER’S MANUAL 8- 35...
Page 251 ‡Add Calculate Immediate Address Time NOTE: A bit field of 32 bits may span five bytes that require two operand cycles to access or may span four bytes that require only one operand cycle to access. 8-36 M68020 USER’S MANUAL MOTOROLA...
Page 252 6(0/0/0) 7(0/1/0) Bcc.L (Not Taken) 3(0/0/0) 6(0/0/0) 9(0/2/0) DBcc (cc = False, Count Not Expired) 3(0/0/0) 6(0/0/0) 9(0/2/0) DBcc (cc = False, Count Expired) 7(0/0/0) 10(0/0/0) 10(0/3/0) DBcc (cc = True) 3(0/0/0) 6(0/0/0) 7(0/1/0) MOTOROLA M68020 USER’S MANUAL 8- 37...
Page 253 12(1/2/0) UNLK 5(1/0/0) 6(1/0/0) 7(1/1/0) n—Number of Operand Transfers Required %—Add Jump Effective Address Time Add Fetch Effective Address Time Add Fetch Immediate Address Time †Add Calculate Effective Address Time ‡Add Calculate Immediate Address Time 8-38 M68020 USER’S MANUAL MOTOROLA...
Page 254 5(0/1/0) TRAPcc.W (Trap) 23(1/0/5) 25(1/0/5) 33(1/3/5) TRAPcc.W (No Trap) 3(0/0/0) 6(0/0/0) 7(0/1/0) TRAPcc.L (Trap) 23(1/0/5) 25(1/0/5) 33(1/3/5) TRAPcc.L (No Trap) 5(0/0/0) 8(0/0/0) 10(0/2/0) TRAPV (Trap) 23(1/0/5) 25(1/0/5) 32(1/2/5) TRAPV (No Trap) 1(0/0/0) 4(0/0/0) 5(0/1/0) MOTOROLA M68020 USER’S MANUAL 8- 39...
Page 255 RTE (Six Word) 20(4/0/0) 21(4/0/0) 24(4/2/0) RTE (Throwaway) 15(4/0/0) 16(4/0/0) 39(4/0/0) RTE (Coprocessor) 31(7/0/0) 32(7/0/0) 33(7/1/0) RTE (Short Fault) 42(10/0/0) 43(10/0/0) 45(10/2/0) RTE (Long Fault) 91(24/0/0) 92(24/0/0) 94(24/2/0) Add the time for RTE on second stack frame. 8-40 M68020 USER’S MANUAL MOTOROLA...
Page 256 80-bit extended-precision real data format. The interface of the MC68020/EC020 to the MC68881 or MC68882 is easily tailored to system cost/performance needs. The MC68020/EC020 and the MC68881/MC68882 communicate via standard asynchronous M68000 bus cycles.
Page 257 Figure 9-1. 32-Bit Data Bus Coprocessor Connection The chip select ( CS ) decode circuitry is asynchronous logic that detects when a particular floating-point coprocessor is addressed. The MC68020/EC020 signals used by the logic include FC2–FC0 and A19–A13. Refer to Section 7 Coprocessor Interface Description for more information concerning the encoding of these signals.
Page 258 The major concern of a system designer is to design a CS interface that meets the AC electrical specifications for both the MC68020/EC020 (MPU) and the MC68881/MC68882 (FPCP) without adding unnecessary wait states to FPCP accesses. The following maximum specifications (relative to CLK low) meet these objectives: low to AS low ≤...
Page 259 PAL16L8 FPCP CS GENERATION CIRCUITRY FOR 25 MHz OPERATION MOTOROLA INC., AUSTIN, TEXAS INPUTS: OUTPUTS: CLKD !~CS = FC2 *FC1 *FC0 ;cpu space = $7 *!A19 *!A18 *A17 *!A16 ;coprocessor access = $2 *!A15 *!A14 *A13 ;coprocessor id = $1 *!CLK ;qualified by MPU clock low...
Page 260 8-, 16-, or 32-bit data port, regardless of alignment. This feature allows the programmer to write code that is not bus-width specific. When accessed, the peripheral or memory subsystem reports its actual port size to the controller, and the MC68020/EC020 then dynamically sizes the data transfer accordingly, using multiple bus cycles when necessary.
Page 261 To satisfy this requirement, the R/ W signal must be included in the byte select logic for the MC68020/EC020. Figure 9-5 shows a block diagram of an MC68020/EC020 system with a single memory bank. The PAL provides memory-mapped byte select signals for an asynchronous 32-bit port and unmapped byte select signals for other memory banks or ports.
Page 262 LMDB UMDB A21–A18 MC74F32 UUDB MC74F32 MC74F32 MC74F32 A31–A2 D31–D0 32-BIT PORT A31–A2 MCM60256A MCM60256A MCM60256A MCM60256A D7–D0 D15–D8 D23–D16 D31–D24 For the MC68EC020, A23–A2. Figure 9-5. Example MC68020/EC020 Byte Select PAL System Configuration MOTOROLA M68020 USER’S MANUAL 9- 7...
Page 263 PAL16L8 BYTE_SELECT MC68020/EC020 BYTE DATA SELECT GENERATION FOR 32-BIT PORTS, MAPPED AND UNMAPPED. MOTOROLA INC., AUSTIN, TEXAS INPUTS: SIZ0 SIZ1 ~CPU OUTPUTS: ~UUDA ~UMDA ~LMDA ~LLDA ~UUDA ~UMDB ~LMDB ~LLDB !~UUDA = RW ;enable upper byte on read of 32-bit port +!A0 *!A1 ;directly addressed, any size...
Page 264 Motorola recommends using a capacitor in the range of 0.01 µF to 0.1 µF on each V pin on each device to provide filtering for most frequencies prevalent in a digital system. In addition to the individual decoupling, several bulk decoupling capacitors should be placed onto the printed circuit board with typical values in the range of 33 µF to 330 µF.
Page 265 9.4 CLOCK DRIVER The MC68020/EC020 is designed to sustain high performance while using low-cost memory subsystems. The MC68020/EC020 requires a stable clock source that is free of ringing and ground bounce, has sufficient rise and fall times, and meets the minimum and maximum high and low cycle times.
Page 266 Figure 9-8. Alternate Clock Solution 9.5 MEMORY INTERFACE The MC68020/EC020 is capable of running an external bus cycle in a minimum of three clocks (refer to Section 5 Bus Operation). The MC68020/EC020 runs an asynchronous bus cycle, terminated by the DSACK1/DSACK0 signals, and has a minimum duration of three controller clock periods in which up to four bytes (32 bits) are transferred.
Page 267 The timing paths that are critical in any memory interface are illustrated and defined in Figure 9-9. The type of device that is interfaced to the MC68020/EC020 determines exactly which of the paths is most critical. The address-to-data paths are typically the critical paths for static devices since there is no penalty for initiating a cycle to these devices and later validating that access with the appropriate bus control signal.
Page 268 Figure 9-9. Access Time Computation Diagram MOTOROLA M68020 USER’S MANUAL 9- 13...
Page 269 (both numbers vary with the actual clock frequency). However, many local memory systems do not operate in a truly asynchronous manner because either the memory control logic can be related to the MC68020/EC020 clock or worst-case propagation delays are known; thus, asynchronous setup times for the DSACK1 / DSACK0 signals can be guaranteed.
Page 270 Another way to optimize the CPU-to-memory access times in a system is to use a clock frequency less than the rated maximum of the specific MC68020/EC020 device. Table 9-5 provides calculated t (see Equation 9-7 of Table 9-4) results for a 16 MHz A V D V MC68020/EC020 and a 25 MHz MC68020/EC020 operating at various clock frequencies.
Page 271 The opt field specifies how arguments are to be passed to the called module; the MC68020/EC020 recognizes only the options of 000 and 100; all others cause a format exception. The 000 option indicates that the called module expects to find arguments from the calling module on the stack just below the module stack frame.
Page 272 TYPE SAVED ACCESS LEVEL CONDITION CODES ARGUMENT COUNT (RESERVED) +$08 MODULE DESCRIPTION POINTER +$0C SAVED PROGRAM COUNTER +$10 SAVED MODULE DATA AREA POINTER +$18 ARGUMENTS (OPTIONAL) Figure 9-12. Module Call Stack Frame MOTOROLA M68020 USER’S MANUAL 9- 17...
Page 273 9.8 ACCESS LEVELS The MC68020/EC020 module mechanism supports a finer level of access control beyond the distinction between user and supervisor privilege levels. The module mechanism allows a module with limited access rights to call a module with greater access rights. With...
Page 274 If opt is equal to 000 (arguments passed on the stack) in the module descriptor, the MC68020/EC020 does not save the stack pointer or load a new stack pointer value. The processor uses the module entry word to save and load the module data area pointer register and then begins execution of the called module.
Page 275 If the called module does not wish the saved module data pointer to be loaded into a register, the RTM instruction word can select register A7, and the loaded value will be overwritten with the correct stack pointer value after the module stack frame is deallocated. 9-20 M68020 USER’S MANUAL MOTOROLA...
Page 276 This section provides the thermal characteristics and electrical specifications for the MC68020/EC020. Note that the thermal and DC electrical characteristics are listed separately for the MC68020 and the MC68EC020. All other data applies to both the MC68020 and the MC68EC020 unless otherwise noted.
Page 277 10.2.1 MC68020 Thermal Characteristics and DC Electrical Characteristics MC68020 Thermal Resistance (°C/W) The following table provides thermal resistance characteristics for junction to ambient and junction to case for the MC68020 packages with natural convection and no heatsink. θ θ Characteristic—Natural Convection and No Heatsink...
Page 278 (°C)—No Heatsink Values for thermal resistance presented in this document were derived using the procedure described in Motorola Reliability Report 7843, “Thermal Resistance Measurement Method for MC68XX Microcomponent Devices,” and are provided for design purposes only. Thermal measurements are complex and dependent on procedure and setup.
Page 279 MC68020 DC Electrical Characteristics ± 5%; GND = 0 V = 5.0 V ; T emperature within defined ranges) Characteristics Symbol Unit Input High Voltage Input Low Voltage –0.5 µA BERR , BR , BGACK , CLK, IPL2 – IPL0 , Input Leakage Current GND ≤...
Page 280 The measurement of the AC specifications is defined by the waveforms shown in Figure 10-1. To test the parameters guaranteed by Motorola, inputs must be driven to the voltage levels specified in Figure 10-1. Outputs are specified with minimum and/or maximum limits, as appropriate, and are measured as shown in Figure 10-1.
Page 281 Figure 10-1. Drive Levels and Test Points for AC Specifications 10-6 M68020 USER’S MANUAL MOTOROLA...
Page 282 — — — — These specifications represent an improvement over previously published specifications for the 25-MHz MC68020 and are valid only for products bearing date codes of 8827 and later. Figure 10-2. Clock Input Timing Diagram MOTOROLA M68020 USER’S MANUAL...
Page 283 — — — Data-In Valid to Clock Low (Setup) (Read) — — — — Late BERR/HALT Asserted to Clock Low — — — — (Setup) AS, DS Negated to DSACK≈, BERR, HALT , AVEC Negated 10-8 M68020 USER’S MANUAL MOTOROLA...
Page 284 — Clks This specification does not apply to the MC68EC020. These specifications represent an improvement over previously published specifications for the 25-MHz MC68020 and are valid only for product bearing date codes of 8827 and later. MOTOROLA M68020 USER’S MANUAL...
Page 285 10. These specifications allow system designers to guarantee that an alternate bus master has stopped driving the bus when the MC68020/EC020 regains control of the bus after an arbitration sequence. 11. This specification allows system designers to qualify the CS signal of an MC68881/MC68882 with AS (allowing 7 ns for a gate delay) and still meet the CS to DS setup time requirement (specification 8B of MC68881UM/AD, MC68881/MC68882 Floating-Point Coprocessor User's Manual) .
Page 286 Figure 10-3. Read Cycle Timing Diagram MOTOROLA M68020 USER’S MANUAL 10-11...
Page 287 Figure 10-4. Write Cycle Timing Diagram 10-12 M68020 USER’S MANUAL MOTOROLA...
Page 288 Figure 10-5. Bus Arbitration Timing Diagram MOTOROLA M68020 USER’S MANUAL 10-13...
Page 289 SECTION 11 ORDERING INFORMATION AND MECHANICAL DATA This section contains the pin assignments and package dimensions of the MC68020 and the MC68EC020. In addition, detailed information is provided to be used as a guide when ordering. 11.1 STANDARD ORDERING INFORMATION 11.1.1 Standard MC68020 Ordering Information...
Page 290 11.2 PIN ASSIGNMENTS AND PACKAGE DIMENSIONS 11.2.1 MC68020 RC and RP Suffix—Pin Assignment D31 D28 D25 D22 D20 D17 GND D14 D12 D9 DS D29 D26 D24 D21 D18 D16 D13 D10 D6 AS R/W D30 D27 D23 D19 GND D15 D11 D7 GND D3...
Page 291 11.2.2 MC68020 RC Suffix—Package Dimensions RC SUFFIX CASE 791-01 MC68020 1 2 3 4 5 6 7 8 9 10 11 12 13 φ NOTES: MILLIMETERS INCHES 1. A AND B ARE DATUMS AND T IS A DATUM SURFACE. 2. POSITIONAL TOLERANCE FOR LEADS (114 PLACES).
Page 292 11.2.3 MC68020 RP Suffix—Package Dimensions RP SUFFIX CASE 789E-02 MC68020 1 2 3 4 5 6 7 8 9 10 11 12 13 114 PL φ 0.76 (0.030) M T A S φ 0.25 (0.010) 0.17 (0.007) NOTES: MILLIMETERS INCHES 1.
Page 293 It is recommended that all pins be connected to power and ground as indicated. NC pins are reserved by Motorola for future use and should have no external connection.
Page 294 11.2.5 MC68020 FC Suffix—Package Dimensions FC SUFFIX CASE 831A-01 MC68020 0.25 (0.010) 0.05 (0.002) 0.20 (0.008) PIN 1 INDE 0.20 (0.008) 0.25 (0.010) 0.05. (0.002) .10 (0.004) SEATING PLANE 132 PL 0.20 (0.008) SECTION P-P NOTES: MILLIMETERS INCHES 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
Page 295 11.2.6 MC68020 FE Suffix—Package Dimensions FE SUFFIX CASE 831-01 MC68020 0.20 (0.008) — Y 0.51 (0.020) — Y PIN 1 INDENT 0.51 (0.020) — Y 0.20 (0.008) — Y ∩ 0.10 (0.004) SEATING PLANE 132 PL 0.20 (0.008) — Y...
Page 296 It is recommended that all pins be connected to power and ground as indicated. Group V CC Address Bus B7, C7 A1, A7, C8, D13 Data Bus K12, M9, N9 J13, L8, M1, M8 Logic D1, D2, E12, E13 F11, F12, J1, J2 Clock — 13-8 MC68838 USER’S MANUAL MOTOROLA...
Page 297 3. DIMENSION D INCLUDES LEAD FINISH. 34.04 35.05 1.340 1.380 2.92 3.18 0.115 0.135 0.44 0.55 0.017 0.022 2.54 BSC 0.100 BSC 3.55 0.120 0.140 3.05 1.02 1.52 0.040 0.060 4.32 4.83 0.170 0.190 30.48 BSC 1.200 BSC MOTOROLA MC68838 USER’S MANUAL 13-9...
Page 298 It is recommended that all pins be connected to power and ground as indicated. NC pins are reserved by Motorola for future use and should have no external connection.
Page 299 LOCATED ON THE LOWER RADIUS OR THE FOOT. 0.325 BSC 0.013 BSC ° ° ° ° 0.25 0.35 0.010 0.014 23.65 24.15 0.931 0.951 — — 0.13 0.005 ° ° — — 17.65 18.15 0.695 0.715 MOTOROLA MC68838 USER’S MANUAL 13-11...
Page 300 Figure A-1 shows a method by which this can be achieved. MC68EC020 BGACK 74LS08 BGACK (DMA) (MC68EC020) 74LS04 (DMA) (DMA) 74LS04 74F74 (MC68EC020) +5 V Figure A-1. Bus Arbitration Circuit— MC68EC020 (Two-Wire) to DMA (Three-Wire) MOTOROLA M68020 USER’S MANUAL A- 1...
Page 301 Control Instructions, 8-38 Bus, 5-24 Coprocessor, 6-25, 7-1 Arbitration, 5-62 Classification, 7-4 Cycles, 5-1 Communication Protocol, 7-4 Master, 5-1 Conditional Instruction Category, 7-10 Operation, 5-1, 5-24 Coprocessor Context Restore Instruction Bus Arbitration (MC68020), 5-63 Category, 7-22 MOTOROLA M68020 USER’S MANUAL INDEX-1...
Page 302 MC68020, 10-4 Instruction, 6-25, 7-3 MC68EC020, 10-5 Instruction Execution, 7-6 Destination Function Code Register (DFC), 1-7 Coprocessor Detected Differences between MC68020 and MC68EC020, Data-Processing-Related Exceptions, 7-51 1-1, 5-62 Exception, 7-49 Double Bus F ault, 5-60 Format Errors, 7-52 DS Signal, 3-4, 5-4, 5-21...
Page 303 Interrupt Acknowledge Cycle, 5-46 cpTRAPcc, 7-15, 7-55 Long-Word Read Cycle, 5-26 Exception-Related, 8-39 MC68EC020 Bus A rbitration, 5-70 Illegal Instruction, 6-7 MC68020 Bus A rbitration, 5-63 MOVE, 8-20 Read-Modify-Write Cycle, 5-39 MOVE SR, 8-3 Reset Exception, 6-4 MOVEA, 8-20 Write Cycle, 5-33...
Page 304 — L — — P — Long-Word Operand, 5-10, 5-14 Package Dimensions Long-Word Read C ycle, 5-26 MC68020 FC Suffix, 11-6 Long-Word Write Cycle, 5-33 MC68020 FE Suffix, 11-7 MC68020 RC Suffix, 11-3 — M — MC68020 RP Suffix, 11-4...
Page 305 RMC Signal, 3-4, 5-3, 5-39 Source Function Code Register (SFC), 1-7 RTE Instruction, 6-19, 6-24 Special-Purpose MOVE Instruction, 8-29 RTM Instruction, 9-14, 9-16, 9-19 Special Status Word (SSW), 6-21 R/ W Signal, 3-4, 5-2, 5-3, 9-5 Spurious Interrupt, 5-48 MOTOROLA M68020 USER’S MANUAL INDEX-5...
Page 306 TAS Instruction, 5-39 — V — Thermal Characteristics, 10-1 Connections, 3-7, 9-9 MC68020, 10-2 Vector Base Register (VBR), 1-7, 2-5, 6-2 MC68020 CQFP Package, 10-2 Virtual Machine, 1-12 MC68EC020, 10-4 Virtual Memory, 1-10 MC68EC020 PQFP Package, 10-4 Thermal Resistance, 10-2, 10-4 —...
Page 307 MOTOROLA MC68030 ENHANCED 32-BIT MICROPROCESSOR USER’S MANUAL Third Edition © MOTOROLA INC., 1992...
Page 308 Systems designers need some knowledge of all sections, with particular emphasis on Sections 1, 5, 6, 7, 13, 14, and Appendix A. Designers who implement a coprocessor for their system also need a thorough knowledge of Section 10. MOTOROLA MC68030 USER’S MANUAL xxiii...
Page 309 Family members and those who are not familiar with these microprocessors. Users of the other family members can find references to similarities to and differences from the other Motorola microprocessors throughout the manual. However, Section 1 and Appendix A specifically identify the MC68030 within the rest of the family and contrast its differences.
Page 310 Immediate Data ........2-21 Effective Address Encoding Summary ......2-22 MOTOROLA MC68030 USER’S MANUAL...
Page 311 Exception Processing........4-6 xxvi MC68030 USER’S MANUAL MOTOROLA...
Page 312 Pipeline Refill (REFILL) ........5-10 5.11.4 Internal Microsequencer Status (STATUS) ....5-10 MOTOROLA MC68030 USER’S MANUAL xxvii...
Page 313 Dynamic Bus Sizing........7-6 xxviii MC68030 USER’S MANUAL MOTOROLA...
Page 314 Address, Size, and Data Bus Relationships ....7-22 7.2.5 MC68030 versus MC68020 Dynamic Bus Sizing ....7-24 7.2.6 Cache Filling .
Page 315 Long-Format Indirect Descriptor ......9-27 9.5.1.11 Short-Format Indirect Descriptor ......9-27 MC68030 USER’S MANUAL MOTOROLA...
Page 316 Bus Error Handler Routine ....... 9-82 Section 10 Coprocessor Interface Description xxxi MC68030 USER’S MANUAL MOTOROLA...
Page 317 Save CIR ..........10-30 xxxii MC68030 USER’S MANUAL MOTOROLA...
Page 318 Trace Exceptions ........10-70 MOTOROLA MC68030 USER’S MANUAL...
Page 319 Bit Field Manipulation Instructions......11-47 11.6.15 Conditional Branch Instructions......11-48 xxxiv MC68030 USER’S MANUAL MOTOROLA...
Page 320 Applications Information 12.1 Adapting the MC68030 to MC68020 Designs ....12-1 12.1.1 Signal Routing ......... 12-2 12.1.2...
Page 321 Package Dimensions ........14-4 Appendix A M68000 Family Summary xxxvi MC68030 USER’S MANUAL MOTOROLA...
Page 322 DSACKx Port ..........6-15 MOTOROLA MC68030 USER’S MANUAL...
Page 323 Synchronous Write Cycle Flowchart ......7-52 7-34 Synchronous Write Cycle with Wait States — CIOUT Asserted ..7-53 xxxviii MC68030 USER’S MANUAL MOTOROLA...
Page 324 Breakpoint Instruction Flowchart ....... . 8-23 MOTOROLA MC68030 USER’S MANUAL...
Page 325 Translation Control Register (TC) Format ......9-54 9-37 Transparent Translation Register (TT0 and TT1) Format ... . . 9-57 MC68030 USER’S MANUAL MOTOROLA...
Page 326 Register Select Mask Format ........10-52 10-37 Transfer Multiple Coprocessor Registers Primitive Format ... . 10-53 MOTOROLA MC68030 USER’S MANUAL...
Page 327 Processor Activity – Odd Alignment ......11-10 12-1 Signal Routing for Adapting the MC68030 to MC68020 Designs ..12-2 12-2 32-Bit Data Bus Coprocessor Connection .
Page 328 Exception Priority Groups ........8-24 MOTOROLA MC68030 USER’S MANUAL...
Page 329 GND Pin Assignments....... . . 12-46 xliv MC68030 USER’S MANUAL MOTOROLA...
Page 330 In addition to instruction execution, the internal caches, the on-chip MMU, and the external bus controller all operate in parallel. The MC68030 fully supports the nonmultiplexed bus structure of the MC68020, with 32 bits of address and 32 bits of data. The MC68030 bus has an enhanced controller that supports both asynchronous and synchronous bus cycles and burst data transfers.
Page 331 Introduction Figure 1-1. Block Diagram MC68030 USER’S MANUAL MOTOROLA...
Page 332 Introduction 1.1 FEATURES The features of the MC68030 microprocessor are: • Object Code Compatible with the MC68020 and Earlier M68000 Microprocessors • Complete 32-Bit Nonmultiplexed Address and Data Buses • 16 32-Bit General-Purpose Data and Address Registers • Two 32-Bit Supervisor Stack Pointers and 10 Special-Purpose Control Registers •...
Page 333 Introduction 1.2 MC68030 EXTENSIONS TO THE M68000 FAMILY In addition to the on-chip instruction cache present in the MC68020, the MC68030 has an internal data cache. Data that is accessed during read cycles may be stored in the on-chip cache, where it is available for subsequent accesses. The data cache reduces the number of external bus cycles when the data operand required by an instruction is already in the data cache.
Page 334 MC68030 is new to the family supervisor programming model for the MC68030 and the two translation registers are new additions to the family supervisor programming model for the MC68030. Only supervisor code uses this feature, and user application programs remain unaffected. MOTOROLA MC68030 USER’S MANUAL...
Page 335 All of the 16 general-purpose registers (D0–D7, A0–A7) may be used as index registers. 16 15 DATA REGISTERS 16 15 ADDRESS REGISTERS 16 15 USER STACK A7 (USP) POINTER PROGRAM COUNTER CONDITION CODE REGISTER Figure 1-2. User Programming Model MC68030 USER’S MANUAL MOTOROLA...
Page 336 3. Master or interrupt mode (M) The vector base register (VBR) contains the base address of the exception vector table in memory. The displacement of an exception vector is added to the value in this register to access the vector table. MOTOROLA MC68030 USER’S MANUAL...
Page 337 I/O space without disturbing the context of the on-chip address translation cache or incurring delays associated with translation table lookups. This feature is useful to graphics, controller, and real-time applications. MC68030 USER’S MANUAL MOTOROLA...
Page 338 The program counter relative mode also has index and offset capabilities. As in the MC68020, both modes are extended to provide indirect reference through memory. In addition to these addressing modes, many instructions implicitly specify the use of the condition code register, stack pointer, and/or program counter.
Page 339 16 or 32 bits. = Program Counter (data) = Immediate value of 8, 16, or 32 bits = Effective Address = Use as indirect access to long-word address. 1-10 MC68030 USER’S MANUAL MOTOROLA...
Page 340 When the bus error handler has completed execution, it returns control to the program that was executing when the error was detected, reruns the faulted bus cycle (when required), and continues the suspended instruction. MOTOROLA MC68030 USER’S MANUAL 1-11...
Page 341 Trap on Overflow LSL, LSR Logical Shift Left and Right TRAPV Test on Overflow MOVE Move Test Operand MOVEA Move Address UNLK Unlink MOVE CCR Move Condition Code Register UNPK Unpack BCD MOVE SR Move Status Register 1-12 MC68030 USER’S MANUAL MOTOROLA...
Page 342 Control and data registers for the virtual device are simulated in the memory map. An access to a virtual register causes a fault and the function of the register is emulated by software. MOTOROLA MC68030 USER’S MANUAL 1-13...
Page 343 Memory management assigns a physical base address to a logical page. The system software then transfers data between secondary storage and memory one or more pages at a time. 1-14 MC68030 USER’S MANUAL MOTOROLA...
Page 344 However, writing data that is not in the cache may or may not cause the data item to be stored in the cache, depending on the write allocation policy selected in the cache control register (CACR). MOTOROLA MC68030 USER’S MANUAL 1-15...
Page 345 Coprocessors are designed to support special computation models that require very specific but widely varying data operand types and sizes. Hence, coprocessor instructions can specify operands of any size. MOTOROLA MC68030 USER’S MANUAL...
Page 346 BCD format, a byte contains one digit; the four least significant bits contain the binary value and the four most significant bits are undefined. Each byte of the packed BCD format contains two digits; the least significant four bits contain the least significant digit. MC68030 USER’S MANUAL MOTOROLA...
Page 347 Note: If width + offset < 32, bit ﬁled wraps around within the register. Unpacked BCD (a = MSB) Packed BCD (a = MSB First Digit, e = MSB Second Digit) Data Organization in Data Registers MOTOROLA MC68030 USER’S MANUAL...
Page 348 The status register (SR), shown in Figure 1–4, is 16 bits wide. Only 12 bits of the status register are defined; all undefined values are reserved by Motorola for future definition. The undefined bits are read as zeros and should be written as zeros for future compatibility. The lower byte of the status register is the CCR.
Page 349 MC68030 does not require data to be aligned on word boundaries (refer to Figure 2–2), but the most efficient data transfers occur when data is aligned on the same byte boundary as its operand size. However, instruction words must be aligned on word boundaries. MOTOROLA MC68030 USER’S MANUAL...
Page 350 BYTE $00000003 LONG WORD $00000004 WORD $00000004 WORD $00000006 BYTE $00000004 BYTE $00000005 BYTE $00000006 BYTE $00000007 LONG WORD $FFFFFFFC WORD $FFFFFFFC WORD $FFFFFFFE BYTE $FFFFFFFC BYTE $FFFFFFFD BYTE $FFFFFFFE BYTE $FFFFFFFF Figure 2-1. Memory Operand Address MC68030 USER’S MANUAL MOTOROLA...
Page 351 PACKED BINARY-CODED DATA BYTE n - 1 BYTE n + 1 BYTE n + 2 ADDRESS UNPACKED BINARY-CODED DATA BYTE n - 1 BYTE n + 2 ADDRESS XX = USER DEFINED VALUE Figure 2-2. Memory Data Organization MOTOROLA MC68030 USER’S MANUAL...
Page 352 EFFECTIVE ADDRESS MODE REGISTER Figure 2-3. Single Effective Address Many instructions imply the addressing mode for one of the operands. The formats of these instructions include appropriate fields for operands that use only one addressing mode. MC68030 USER’S MANUAL MOTOROLA...
Page 353 In the data register direct mode, the operand is in the data register specified by the effective address register field. GENERATION: EA = Dn ASSEMBLER SYNTAX: MODE: REGISTER: DATA REGISTER: OPERAND OPERAND NUMBER OF EXTENSION WORDS: MOTOROLA MC68030 USER’S MANUAL...
Page 354 GENERATION: EA = (An) An = An + SIZE ASSEMBLER SYNTAX: (An) + MODE: REGISTER: MEMORY ADDRESS ADDRESS REGISTER: OPERAND LENGTH ( 1, 2, OR 4): MEMORY ADDRESS: OPERAND NUMBER OF EXTENSION WORDS: 2-10 MC68030 USER’S MANUAL MOTOROLA...
Page 355 GENERATION: An = An – SIZE EA = (An) ASSEMBLER SYNTAX: – (An) MODE: REGISTER: MEMORY ADDRESS ADDRESS REGISTER: OPERAND LENGTH (1, 2, OR 4): MEMORY ADDRESS: OPERAND NUMBER OF EXTENSION WORDS: 0 MOTOROLA MC68030 USER’S MANUAL 2-11...
Page 356 EA = (An) + (XN) + d (d ,An,Xn.SIZE*SCALE) ASSEMBLER SYNTAX: MODE: REGISTER: ADDRESS REGISTER: MEMORY ADDRESS DISPLACEMENT: SIGN EXTENDED INTEGER INDEX REGISTER SIGN-EXTENDED VALUE SCALE: SCALE VALUE MEMORY ADDRESS: OPERAND NUMBER OF EXTENSION WORDS: 2-12 MC68030 USER’S MANUAL MOTOROLA...
Page 357 EA = (An) + (Xn) + bd ASSEMBLER SYNTAX: (bd,An,Xn.SIZE*SCALE) MODE: REGISTER: ADDRESS REGISTER: MEMORY ADDRESS BASE DISPLACEMENT: SIGN-EXTENDED VALUE INDEX REGISTER: SIGN-EXTENDED VALUE SCALE: SCALE VALUE MEMORY ADDRESS: OPERAND NUMBER OF EXTENSION WORDS: 1,2, OR 3 MOTOROLA MC68030 USER’S MANUAL 2-13...
Page 358 SIGN-EXTENDED VALUE INDIRECT MEMORY ADDRESS POINTS TO VALUE AT INDIRECT MEMORY ADDRESS INDEX REGISTER: SIGN-EXTENDED VALUE SCALE VALUE SCALE: OUTER DISPLACEMENT: SIGN-EXTENDED VALUE EFFECTIVE ADDRESS: OPERAND NUMBER OF EXTENSION WORDS: 1,2, 3, 4, OR 5 2-14 MC68030 USER’S MANUAL MOTOROLA...
Page 359 SIGN-EXTENDED VALUE SIGN-EXTENDED VALUE SCALE VALUE INDEX REGISTER: INDIRECT MEMORY ADDRESS POINTS TO SCALE: VALUE AT INDIRECT MEMORY ADDRESS OUTER DISPLACEMENT: SIGN-EXTENDED VALUE EFFECTIVE ADDRESS: OPERAND NUMBER OF EXTENSION WORDS: 1,2, 3, 4, OR 5 MOTOROLA MC68030 USER’S MANUAL 2-15...
Page 360 EA = (PC) + (Xn) + d ASSEMBLER SYNTAX: (d , PC,Xn. SIZE*SCALE) MODE: REGISTER: PROGRAM COUNTER: ADDRESS OF EXTENSION WORD DISPLACEMENT: SIGN EXTENDED INTEGER INDEX REGISTER SIGN-EXTENDED VALUE SCALE: SCALE VALUE MEMORY ADDRESS: OPERAND NUMBER OF EXTENSION WORDS: 2-16 MC68030 USER’S MANUAL MOTOROLA...
Page 361 ASSEMBLER SYNTAX: (bd, PC, Xn. SIZE*SCALE) MODE: REGISTER: PROGRAM COUNTER: ADDRESS OF EXTENSION WORD BASE DISPLACEMENT: SIGN-EXTENDED VALUE INDEX REGISTER SIGN-EXTENDED VALUE SCALE: SCALE VALUE MEMORY ADDRESS: OPERAND NUMBER OF EXTENSION WORDS: 1, 2 OR 3 MOTOROLA MC68030 USER’S MANUAL 2-17...
Page 362 INDIRECT MEMORY ADDRESS POINTS TO VALUE AT INDIRECT MEMORY ADDRESS IN PROGRAM SPACE INDEX REGISTER: SIGN-EXTENDED VALUE SCALE VALUE OUTER DISPLACEMENT: SIGN-EXTENDED VALUE EFFECTIVE ADDRESS: OPERAND NUMBER OF EXTENSION WORDS: 1,2, 3, 4, OR 5 2-18 MC68030 USER’S MANUAL MOTOROLA...
Page 363 INDEX REGISTER SIGN-EXTENDED VALUE SCALE VALUE INDIRECT MEMORY ADDRESS POINTS TO VALUE AT INDIRECT MEMORY ADDRESS IN PROGRAM SPACE OUTER DISPLACEMENT: SIGN-EXTENDED VALUE EFFECTIVE ADDRESS: OPERAND NUMBER OF EXTENSION WORDS: 1, 2, 3, 4 OR 5 MOTOROLA MC68030 USER’S MANUAL 2-19...
Page 364 GENERATION: EA GIVEN ASSEMBLER SYNTAX: (xxx).L MODE: REGISTER FIELD: FIRST EXTENSION WORD: ADDRESS HIGH SECOND EXTENSION WORD: ADDRESS LOW CONCATENATION MEMORY ADDRESS: OPERAND NUMBER OF EXTENSION WORDS: 2-20 MC68030 USER’S MANUAL MOTOROLA...
Page 365 Coprocessor instructions can support immediate data of any size. The instruction word is followed by as many extension words as are required. Generation: Operand given Assembler Syntax: #xxx Mode Field: Register Field: Number of Extension Words: 1 or 2, except for coprocessor instructions MOTOROLA MC68030 USER’S MANUAL 2-21...
Page 366 Indirect Postindexed with Word Outer Displacement Indirect Postindexed with Long Outer Displacement No Memory Indirection Memory Indirect with Mull Outer Displacement Memory Indirect with Word Outer Displacement Memory Indirect with Long Outer Displacement 100–111 Reserved 2-22 MC68030 USER’S MANUAL MOTOROLA...
Page 367 A memory addressing effective address mode is one that refers to memory operands. Alterable An alterable addressing effective address mode is one that refers to alterable (writable) operands. Control A control addressing effective address mode is one that refers to memory operands without an associated size. MOTOROLA MC68030 USER’S MANUAL 2-23...
Page 368 2.6 PROGRAMMER`S VIEW OF ADDRESSING MODES Extensions to the indexed addressing modes, indirection, and full 32-bit displacements provide additional programming capabilities for both the MC68020 and the MC68030. This section describes addressing techniques that exploit these capabilities and summarizes the addressing modes from a programming point of view.
Page 369 (if at all), particularly in programs that require maximum performance. 2.6.1 Addressing Capabilities In both the MC68020 and the MC68030, setting the base register suppress (BS) bit in the full format extension word (see Figure 2–4) suppresses use of the base address register in calculating the effective address.
Page 370 Data Organization and Addressing Capabilities For both the MC68020 and the MC68030, the register indirect modes can be extended further. Since displacements can be 32 bits wide, they can represent absolute addresses or the results of expressions that contain absolute addresses. This allows the general register indirect form to be (bd,Rn) or (bd,An,Rn) when the base register is not suppressed.
Page 371 RECORD OF 8 WORDS (SCALE = 4) (SCALE = 8) A6 = 1 A6 = 1 NOTE: Regardless of array structure, software increments index by the appropriate amount to point to next record. Figure 2-7. Addressing Array Items MOTOROLA MC68030 USER’S MANUAL 2-27...
Page 372 The preindexed indirect mode (see Figure 2–11) uses the contents of An as an index to the pointer list structure at the displacement. Register Xn is the index to the pointer, which contains the address of the data item. 2-28 MC68030 USER’S MANUAL MOTOROLA...
Page 373 Data Organization and Addressing Capabilities SYNTAX: ([An],od) MEMORY STRUCTURE POINTER DATA ITEM Figure 2-9. Accessing an Item in a Structure Using a Pointer SYNTAX: ([bd,An]) POINTER LIST POINTER DATA ITEM Figure 2-10. Indirect Addressing, Suppressed Index Register MOTOROLA MC68030 USER’S MANUAL 2-29...
Page 374 Data Organization and Addressing Capabilities SYNTAX: ([bd,An,Xn]) POINTER LIST DATA ITEM POINTER Figure 2-11. Preindexed Indirect Addressing 2-30 MC68030 USER’S MANUAL MOTOROLA...
Page 375 SYNTAX: ([bd,An],Xn) POINTER LIST POSTINDEXED STRUCTURE DATA ITEM POINTER Figure 2-12. Postindexed Indirect Addressing SYNTAX: ([bd,An,Xn],od) POINTER LIST STRUCTURE DATA ITEM POINTER Figure 2-13. Preindexed Indirect Addressing with Outer Displacement MOTOROLA MC68030 USER’S MANUAL 2-31...
Page 376 If the displacement is 16 bits or less, the address register indirect with displacement mode (d ,An) is used. When a 32- bit displacement is required, the address register indirect with index (bd,An,Xn) is used with the index register suppressed. 2-32 MC68030 USER’S MANUAL MOTOROLA...
Page 377 MC68030 architecture, are as follows: Immediate Data — #data: The data is a constant located in the instruction stream. Register Direct — Rn: The contents of a register contain the operand. Scanning Modes: (An)+ MOTOROLA MC68030 USER’S MANUAL 2-33...
Page 378 Absolute address with two variable indexes. Subscripting: (An,Rn*scale) Address register pointer subscript. (disp,An,Rn*scale) Address register pointer subscript with constant displacement (or base address with subscript). (addr,Rn*scale) Absolute address with subscript. (addr,An,Rn*scale) Absolute address subscript with variable index. Program Relative: 2-34 MC68030 USER’S MANUAL MOTOROLA...
Page 379 ([preindexed],disp) Memory pointer as base with displacement to data operand. ([postindexed],Rn) Memory pointer with variable index. ([postindexed],disp,Rn) Memory pointer with constant and variable index. ([postindexed],Rn*scale) Memory pointer subscripted. ([postindexed],disp,Rn*scale) Memory pointer subscripted with constant index. MOTOROLA MC68030 USER’S MANUAL 2-35...
Page 380 MC68030 microprocessors are shown in Figure 2–15. Notice the encoding for SCALE used by the MC68020/MC68030 is a compatible extension of the M68000 architecture. A value of zero for SCALE is the same encoding for both extension words; hence, software that uses this encoding is both upward and downward compatible across all processors in the product line.
Page 381 In long-word-organized memory, aligning the stack pointer on a long-word address signed significantly increases the efficiency of stacking exception frames, subroutine calls and returns, and other stacking operations. MOTOROLA MC68030 USER’S MANUAL 2-37...
Page 382 LOW MEMORY (FREE) TOP OF STACK BOTTOM OF STACK HIGH MEMORY To implement stack growth from low to high memory, use: (An)+ to push data on the stack, –An to pull data from the stack. 2-38 MC68030 USER’S MANUAL MOTOROLA...
Page 383 To implement the queue as a circular buffer, the relevant address register should be checked and adjusted, if necessary, before performing the "put'' or "get'' operation. The address register is adjusted by subtracting the buffer length (in bytes) from the register. MOTOROLA MC68030 USER’S MANUAL 2-39...
Page 384 To implement the queue as a circular buffer, the "get'' or "put'' operation should be performed first, and then the relevant address register should be checkout and adjusted, if necessary. The address register is adjusted by adding the buffer length (in bytes) to the register contents. 2-40 MC68030 USER’S MANUAL MOTOROLA...
Page 385 SPECIAL OPERAND SPECIFIERS (IF ANY, ONE OR TWO WORDS) IMMEDIATE OPERAND OR SOURCE EFFECTIVE ADDRESS EXTENSION( IF ANY, ONE TO SIX WORDS) DESTINATION EFFECTIVE ADDRESS EXTENSION (IF ANY, ONE TO SIX WORDS) Figure 3-1. Instruction Word General Format MOTOROLA MC68030 USER’S MANUAL...
Page 386 The instructions form a set of tools to perform the following operations: Data Movement Bit Field Manipulation Integer Arithmetic Binary-Coded Decimal Arithmetic Logical Program Control Shift and Rotate System Control Bit Manipulation Multiprocessor Communications Each instruction type is described in detail in the following paragraphs MC68030 USER’S MANUAL MOTOROLA...
Page 387 = list of registers, for example D3 — D0 # 〈 data 〉 = immediate data; a literal integer {offset:width} = bit field selection label = assemble program label [m] = bit m of an operand [m:n] = bits m through n of operand MOTOROLA MC68030 USER’S MANUAL...
Page 388 MOVE instructions, there are several special data movement instructions: move multiple registers (MOVEM), move peripheral data (MOVEP), move quick (MOVEQ), exchange registers (EXG), load effective address (LEA), push effective address (PEA), link stack (LINK), and unlink stack (UNLK). MC68030 USER’S MANUAL MOTOROLA...
Page 389 A set of extended instructions provides multiprecision and mixed-size arithmetic. These instructions are add extended (ADDX), subtract extended (SUBX), sign extended (EXT), and negate binary with extend (NEGX). Refer to Table 3–2 for a summary of the integer arithmetic operations. MOTOROLA MC68030 USER’S MANUAL...
Page 390 A similar set of immediate instructions (ANDI, ORI, and EORI) provide these logical operations with all sizes of immediate data. The TST instruction compares the operand with zero arithmetically, placing the result in the condition code register. Table 3–3 summarizes the logical operations. MC68030 USER’S MANUAL MOTOROLA...
Page 391 SWAP instruction exchanges the 16-bit halves of a register. Performance of shift/rotate instructions is enhanced so that use of the ROR and ROL instructions with a shift count of eight allows fast byte swapping. Table 3–4 is a summary of the shift and rotate operations. MOTOROLA MC68030 USER’S MANUAL...
Page 392 Register operands are 32 bits long, and memory operands are 8 bits long. In Table 3–5, the summary of the bit manipulation operations, Z refers to bit 2, the zero bit of the status register. MC68030 USER’S MANUAL MOTOROLA...
Page 393 Field MSB → N; ∼ (OR of all bits in field) → Z BFTST 1 — 32 NOTE: All bit ﬁeld instructions set the N and Z bits as shown for BFTST before performing the speciﬁed operation. MOTOROLA MC68030 USER’S MANUAL...
Page 394 16→8 #〈data〉 destination Dn,Dn,# 〈data〉 16→8 – X → destination SBCD Dn,Dn destination - source –(An),–(An) packed source → unpacked source UNPK –(An) 8→16 unpacked source + immediate data → #〈data〉 Dn,Dn,#〈data〉 8→16 unpacked destination 3-10 MC68030 USER’S MANUAL MOTOROLA...
Page 395 Greater than — Less than — Always true* — Equal — Higher — Minus — Overﬂow clear — Never true* — -Less or equal — Not equal — Overﬂow set *Not applicable to the Bcc instructions. MOTOROLA MC68030 USER’S MANUAL 3-11...
Page 396 Condition Code Register immediate data Λ CCR → CCR ANDI #〈data〉,CCR immediate data ⊕ CCR → CCR EORI #〈data〉,CCR 〈ea〉,CCR source → CCR MOVE CCR → destination CCR,〈ea〉 immediate data V CCR → CCR #〈data〉,CCR 3-12 MC68030 USER’S MANUAL MOTOROLA...
Page 397 〈ea〉 save coprocessor state at 〈ea〉 cpSAVE none 〈ea〉 if cpcc true, then 1's → destination; else 0's → destination cpScc cpTRAPcc none none if cpc true, then TRAPcc exception #〈data〉 16, 32 MOTOROLA MC68030 USER’S MANUAL 3-13...
Page 398 Cleared otherwise. C (carry) Set if a carry out of the most significant bit of the operand occurs for an addition. Also set if a borrow occurs in a subtraction. Cleared otherwise. 3-14 MC68030 USER’S MANUAL MOTOROLA...
Page 399 Z = Z Λ Rm Λ . . . Λ R0 ? V = Dm Λ Rm C = Dm V Rm ? V = Dm Λ Rm NEGX C = Dm V Rm Z = Z Λ Rm Λ . . . Λ R0 MOTOROLA MC68030 USER’S MANUAL 3-15...
Page 400 UB = Upper Bound Z = Rm Λ . . . Λ R0 Λ = Boolean AND Destination Operand — Most Signiﬁcant Bit V = Boolean OR Destination Operand — Most Signiﬁcant Bit Rm = NOT Rm 3-16 MC68030 USER’S MANUAL MOTOROLA...
Page 401 N •V •Z + N • V •Z Greater Than 1110 Z + N •V + N • V Less or Equal 1111 • = Boolean AND + = Boolean OR N = Boolean NOT N *Not available for the Bcc instruction. MOTOROLA MC68030 USER’S MANUAL 3-17...
Page 402 Indicates that the operand register points to the memory (〈address register〉) + — Location of the instruction operand — the optional mode qualifiers are -, +, (d), and (d,ix) #xxx or #〈data〉 — Immediate data that follows the instruction word(s) 3-18 MC68030 USER’S MANUAL MOTOROLA...
Page 403 "else'' clause is present, the opera- tions after "else" are performed. If the condition is false and else is omitted, the instruction performs no operation. Refer to the Bcc instruction description as an example. MOTOROLA MC68030 USER’S MANUAL 3-19...
Page 404 BSET BSET Dn,〈ea〉BSET #〈data〉,〈ea〉 1 → 〈bit number〉 of Destination SP – 4 → SP; PC → (SP); PC + d → PC BSR (label〉 –(〈bit number〉 of Destination) → Z; BTST BTST Dn,〈ea〉BTST #〈data〉,〈ea〉 3-20 MC68030 USER’S MANUAL MOTOROLA...
Page 405 DIVU.W 〈ea〉,Dn32/16 → 16r:16q DIVU DIVU.L 〈ea〉,Dq 32/32 → 32q DIVUL DIVU.L 〈ea〉,Dr:Dq 64/32 → 32r:32q DIVUL.L 〈ea〉,Dr:Dq32/32 → 32r:32q Source ⊕ Destination → Destination EOR Dn,〈ea〉 Immediate Data ⊕ Destination → Destination EORI EORI #〈data〉,〈ea〉 MOTOROLA MC68030 USER’S MANUAL 3-21...
Page 406 Rc → Rn or Rn → Rc MOVEC Rn,Rc else TRAP Registers → Destination MOVEM MOVEM register list,〈ea〉MOVEM Source → Registers 〈ea〉,register list Source → Destination MOVEP MOVEP Dx,(d,Ay) MOVEP (d,Ay),Dx Immediate Data → Destination MOVEQ MOVEQ #〈data〉,Dn 3-22 MC68030 USER’S MANUAL MOTOROLA...
Page 407 If supervisor state RESET then Assert RSTO Line else TRAP Destination Rotated by 〈count〉 → Destination ROL,ROR Rx,Dy #〈data〉,Dy 〈ea〉 Destination Rotated with X by 〈count〉 → Destination ROXL, ROXd Dx,Dy ROXR ROXd #〈data〉,Dy 〈ea〉 ROXd MOTOROLA MC68030 USER’S MANUAL 3-23...
Page 408 ( –). 4. A list of any combination of the three ﬂoating-point system control registers (FPCR, FPSR, and FPIAR) with indvidual register names separated by a slash (/). 5. Where d is direction, L or R. 3-24 MC68030 USER’S MANUAL MOTOROLA...
Page 409 INC_LOOP MOVE.W D0,D1 make a copy of it ADDQ.W #1,D1 and increment it CAS.W D0,D1,SYS_CNTR if countr value is still the same, update it INC_LOOP if not, try again MOTOROLA MC68030 USER’S MANUAL 3-25...
Page 410 IF NOT, TRY AGAIN BEFORE INSERTING AN ELEMENT: ENTRY ENTRY ENTRY + NEXT + NEXT + NEXT HEAD AFTER INSERTING AN ELEMENT: ENTRY ENTRY ENTRY + NEXT + NEXT + NEXT HEAD Figure 3-2. Linked List Insertion 3-26 MC68030 USER’S MANUAL MOTOROLA...
Page 411 (MAY BE NULL) BEFORE DELETING AN ELEMENT: ENTRY ENTRY ENTRY + NEXT + NEXT + NEXT HEAD AFTER DELETING AN ELEMENT: ENTRY ENTRY ENTRY + NEXT + NEXT + NEXT HEAD Figure 3-3. Linked List Deletion MOTOROLA MC68030 USER’S MANUAL 3-27...
Page 412 D1 to the LIST-GET pointer and to the address in register A2. If the pointers have not been updated, the CAS2 instruction loads the address in D2 into the LIST_GET pointer and zero into the address in register A2. 3-28 MC68030 USER’S MANUAL MOTOROLA...
Page 413 DDEMPTY after moving a zero pointer value into D2. This instruction checks the addresses in LIST_PUT and LIST_GET to verify that no other routine has inserted another element or deleted the last element. Then the instruction moves zero into both pointers, and the list is empty. MOTOROLA MC68030 USER’S MANUAL 3-29...
Page 414 When the operand of the instruction is the address of the link address at the bottom of a stack frame, the effect is to remove the stack frame from the stack and from the linked list. 3-30 MC68030 USER’S MANUAL MOTOROLA...
Page 415 However, control register locations are not memory locations; therefore, it is not always possible to insert or extract bit fields of a register without affecting other fields within the register. MOTOROLA MC68030 USER’S MANUAL 3-31...
Page 416 All previous integer instructions and floating-point external operand accesses complete execution before the NOP begins. The NOP instruction does not synchronize the FPU pipeline; floating-point instructions with floating-point register operand destinations can be executing when the NOP begins. MOTOROLA MC68030 USER’S MANUAL 3-32...
Page 417 Only an external reset can restart a halted processor. (When the processor executes a STOP instruction, it is in a special type of normal processing state, one without bus cycles. It is stopped, not halted.) MOTOROLA MC68030 USER’S MANUAL...
Page 418 MSP when a task switch is performed, providing an efficient means for transferring task-related stack items. The other supervisor stack (ISP) can be used for interrupt control information and workspace area as interrupt handling routines require. MC68030 USER’S MANUAL MOTOROLA...
Page 419 To prevent a user program from entering the supervisor privilege level, except in a controlled manner, instructions that can alter the S bit in the status register are privileged. The TRAP #n instruction provides controlled access to operating system services for user programs. MOTOROLA MC68030 USER’S MANUAL...
Page 420 S bit of the restored status register. If the frame on top of the stack was generated by a bus fault (bus error or address error exception), the RTE instruction restores the entire saved processor state from the stack. MC68030 USER’S MANUAL MOTOROLA...
Page 421 The processor uses accesses in this space to communicate with external devices for special purposes. For example, all M68000 processors use the CPU space for interrupt acknowledge cycles. The MC68020 and MC68030 also generate CPU space accesses for breakpoint acknowledge and coprocessor operations.
Page 422 Details of exception processing are provided in Section 8 Exception Processing , and Table 8-1 lists the exception vector assignments. MC68030 USER’S MANUAL MOTOROLA...
Page 423 Figure 4-1. Refer to Section 8 Exception Processing for a complete list of exception stack frames. STATUS REGISTER PROGRAM COUNTER FORMAT VECTOR OFFSET ADDITIONAL PROCESSOR STATE INFORMATION (2, 6, 12, OR 42 WORDS, IF NEEDED) Figure 4-1. General Exception Stack Frame MOTOROLA MC68030 USER’S MANUAL...
Page 424 RESET BUS EXCEPTION HALT MC68EC030 CONTROL BERR SYNCHRONOUS ASYNCHRONOUS STERM BUS CONTROL BUS CONTROL DBEN REFILL EMULATOR DSACK0 STATUS SUPPORT DSACK1 CDIS CIIN CIOUT CACHE (10) CBREQ CONTROL CBACK GND (14) Figure 5-1. Functional Signal Groups MOTOROLA MC68030 USER’S MANUAL...
Page 425 Indicates that valid data is to be placed on the data bus by an external device or has been placed on the data bus by the MC68030. Data Buffer Enable DBEN Provides an enable signal for external data buffers. MC68030 USER’S MANUAL MOTOROLA...
Page 426 Dynamically disables the translation mechanism of the MMU. Pipe Refill REFILL Indicates when the MC68030 is beginning to fill pipeline. Microsequencer Status STATUS Indicates the state of the microsequencer Clock Clock input to the processor. Power Supply Power supply. Ground Ground connection MOTOROLA MC68030 USER’S MANUAL...
Page 427 With A0, A1, DSACK0, DSACK1, and STERM, SIZ0 and SIZ1 define the number of bits transferred on the data bus. Refer to 7.2.1 Dynamic Bus Sizing for more information on the size signals and their use in dynamic bus sizing. MC68030 USER’S MANUAL MOTOROLA...
Page 428 This three-state output indicates that a valid address is on the address bus. The function code, size, and read/write signals are also valid when AS is asserted. Refer to 7.1.3 Address Strobe for information about the relationship of AS to bus operation. MOTOROLA MC68030 USER’S MANUAL...
Page 429 This signal applies only to synchronous operation. Refer to 7.1.7 Bus Cycle Termination Signals for more information about the relationship of STERM to bus operation. MC68030 USER’S MANUAL MOTOROLA...
Page 430 This input signal indicates that the accessed device can operate in the burst mode and can supply at least one more long word for the instruction or data cache. Refer to 7.3.7 Burst Operation Cycles for information about burst mode operation. MOTOROLA MC68030 USER’S MANUAL...
Page 431 This input signal indicates that an external device needs to become the bus master. This is typically a "wire-ORed” input (but does not need to be constructed from open-collector devices). Refer to 7.7 Bus Arbitration for more information. MC68030 USER’S MANUAL MOTOROLA...
Page 432 The bus error signal indicates that an invalid bus operation is being attempted or, when used with HALT, that the processor should retry the current cycle. Refer to 7.5 Bus Exception Control Cycles for a description of the effects of BERR on bus operations. MOTOROLA MC68030 USER’S MANUAL...
Page 433 Refer to Section 12 Applications Information for a description of the use of this signal by an emulator. 5-10 MC68030 USER’S MANUAL MOTOROLA...
Page 434 Information and Mechanical Data describes the groupings of V connections, and Section 12 Applications Information describes a typical power supply interface. 5.14 SIGNAL SUMMARY Table 5-2 provides a summary of the electrical characteristics of the signals discussed in this section. 5-11 MC68030 USER’S MANUAL MOTOROLA...
Page 435 Bus Error BERR Input — Cache Disable CDIS Input — MMU Disable MMUDIS Input — Pipeline Refill REFILL Output Microsequencer Status STATUS Output Clock Input — — Power Supply Input — — Ground Input — — 5-12 MC68030 USER’S MANUAL MOTOROLA...
Page 436 MMU performs logical-to-physical address translation in parallel with the cache lookup in case an external cycle is required. MOTOROLA MC68030 USER’S MANUAL...
Page 437 On-Chip Cache Memories Figure 6-1. Internal Caches and the MC68030 MC68030 USER’S MANUAL MOTOROLA...
Page 438 Therefore, the state of the corresponding CI bits in the MMU are also ignored. The MMU is used to validate all accesses that require external bus cycles; an address translation must be available and valid, protections are checked, and the CIOUT signal is asserted appropriately. MOTOROLA MC68030 USER’S MANUAL...
Page 439 Dynamic RAMs supporting fast access modes (page, nibble, or static column) are easily employed to support the MC68030 burst mode. MC68030 USER’S MANUAL MOTOROLA...
Page 440 A1 is supplied to the instruction pipe. When the address and function code bits do not match or the requested entry is not valid, a miss occurs. The bus controller initiates a long-word prefetch operation for the required MOTOROLA MC68030 USER’S MANUAL...
Page 441 The value in the data cache might be used by another instruction before the external write cycle has completed, although this should not have any adverse consequences. Refer to 7.6 Bus Synchronization for the details of bus synchronization. MC68030 USER’S MANUAL MOTOROLA...
Page 442 Thus, an aligned long-word data write may replace a previously valid entry; whereas, a misaligned data write or a write of data that is not long word may invalidate a previously valid entry or entries. MOTOROLA MC68030 USER’S MANUAL...
Page 443 B) b8-b9 b8'-b9' B) b8-b9 b8'-b9' USER LONG-WORD WRITE OF b6'-b9' to $00001056 (TAG MATCH, LONG-WORD DATA, MISALIGNED, b6-b7 RESULT IN A CACHE MISS, b8-b9 RESULT IN A CACHE HIT) Figure 6-4. No-Write-Allocation and Write-Allocation Mode Examples MC68030 USER’S MANUAL MOTOROLA...
Page 444 8 bits are requested. Similarly, the processor assumes that a 16-bit termination signal indicates that all 16 bits are valid. If the device cannot supply its full port width of data, it must assert CIIN for all bus cycles corresponding to a cache entry. MOTOROLA MC68030 USER’S MANUAL...
Page 445 (if the port size is less than 32 bits) before it requests the remainder of the operand and corresponding long word to fill the second cache entry. If the port size is 32 bits, the processor performs two accesses, one for each cache entry. 6-10 MC68030 USER’S MANUAL MOTOROLA...
Page 446 If the bus error occurs on a read cycle for a portion of the required operand (not the remaining bytes of the cache entry) to be loaded into the data cache, the processor immediately takes a bus error exception. If MOTOROLA MC68030 USER’S MANUAL 6-11...
Page 447 (EU). However, data from the burst fill cycles is not available to the EU until the burst operation is complete. Since the microsequencer makes two separate requests for misaligned data operands, only the first portion of the misaligned operand returned during a 6-12 MC68030 USER’S MANUAL MOTOROLA...
Page 448 CBREQ. During this burst operation, long words $10, $14, $18, and $1C are all filled in that order. (UNABLE TO LOCATE ART) Figure 6-13. Deferred Burst Filling Example MOTOROLA MC68030 USER’S MANUAL 6-13...
Page 449 CBREQ. Once the burst terminates, the microsequencer requests a read cycle for the second portion. Since the burst terminated abnormally for the second cycle of the burst, the data cache 6-14 MC68030 USER’S MANUAL MOTOROLA...
Page 450 MOVEC instruction. For example, loading a long word in which bits 3 and 11 are set into the CACR clears both caches. Bits 31-14 and 7-5 are reserved for Motorola definition. They are currently read as zeros and are ignored when written. For future compatibility, writes should not set these bits.
Page 451 MOVEC instruction loads a one into the CED bit of the CACR, regardless of the states of the ED and FD bits. The CED bit is always read as a zero. 6-16 MC68030 USER’S MANUAL MOTOROLA...
Page 452 The processor clears only the specified long word by clearing the valid bit for the entry at the time a MOVEC instruction loads a one into the CEI bit of the CACR, regardless of the states of the EI and FI bits. The CEI bit is always read as a zero. MOTOROLA MC68030 USER’S MANUAL 6-17...
Page 453 Although only the index field is used currently, all 32 bits of the register are implemented and are reserved for use by Motorola. CACHE FUNCTION ADDRESS INDEX Figure 6-15.
Page 454 Strobe signals, one for the address bus and another for the data bus, indicate the validity of the address and provide timing information for the data. MOTOROLA MC68030 USER’S MANUAL...
Page 455 Bus Operation The bus can operate in an asynchronous mode identical to the MC68020 bus for any port width. The bus and control input signals used for asynchronous operation are internally synchronized to the MC68030 clock, introducing a delay. This delay is the time period required for the MC68030 to sample an asynchronous input signal, synchronize the input to the internal clocks of the processor, and determine whether it is high or low.
Page 456 The function code signals (FC0–FC2) are also driven at the beginning of a bus cycle. These three signals select one of eight address spaces (refer to Table 4-1) to which the address applies. Five address spaces are presently defined. Of the remaining three, one is reserved MOTOROLA MC68030 USER’S MANUAL...
Page 457 Bus Operation for user definition and two are reserved by Motorola for future use. The function code signals are valid while AS is asserted. At the beginning of a bus cycle, the size signals (SIZ0 and SIZ1) are driven along with ECS and the FC0–FC2.
Page 458 These signals also indicate to the processor the size of the port for the bus cycle just completed, as shown in Table 7-1. Refer to 7.3.1 Asynchronous Read Cycle for timing relationships of DSACK0 and DSACK1. MOTOROLA MC68030 USER’S MANUAL...
Page 459 (byte, word, or long word) and indicates completion of the bus cycle to the processor through the use of the DSACKx inputs. Refer to Table 7-1 for DSACKx encodings and assertion results. MC68030 USER’S MANUAL MOTOROLA...
Page 460 OP0, and OP3 is the least significant byte. The two bytes of a word- length operand are OP2 (most significant) and OP3. The single byte of a byte-length operand is OP3. These designations are used in the figures and descriptions that follow. MOTOROLA MC68030 USER’S MANUAL...
Page 461 A0 and A1 indicate the byte offset from the base. Table 7-3 shows the encodings of A0 and A1 and the corresponding byte offsets from the long-word base. MC68030 USER’S MANUAL MOTOROLA...
Page 462 PRn and Nn are not required and can be replaced by “don't cares”. Table 7-2. Size Signal Table 7-3. Address Offset Encoding Encodings SIZ1 SIZ0 Size Offset Byte +0 Bytes Word +1 Byte 3 Bytes +2 Bytes Long Word +3 Bytes MOTOROLA MC68030 USER’S MANUAL...
Page 463 (D16–D31). The bus cycle transfers the remaining bytes to the word-size port. Figure 7- 6 shows the timing of the bus transfer signals for this operation. 7-10 MC68030 USER’S MANUAL MOTOROLA...
Page 464 Table 7-5. MC68030 Internal to External Data Bus. (Table did not make it over in the conversion from Word) LONG WORD OPERAND DATA BUS WORD MEMORY MC68EC030 MEMORY CONTROL SIZ1 SIZ0 DSACK1 DSACK0 Figure 7-5. Example of Long-Word Transfer to Word Port MOTOROLA MC68030 USER’S MANUAL 7-11...
Page 465 Each bus cycle transfers a single byte. The size signals for the first cycle specify two bytes; for the second cycle, one byte. Figure 7-8 shows the associated bus transfer signal timing. 7-12 MC68030 USER’S MANUAL MOTOROLA...
Page 466 For maximum performance, data items should be aligned on their natural boundaries. All instruction words and extension words must reside on word boundaries. Attempting to prefetch an instruction word at an odd address causes an address error exception. MOTOROLA MC68030 USER’S MANUAL 7-13...
Page 467 Bus Operation A31-A2 FC2-FC0 SIZ1 SIZ0 DSACK1 DSACK0 DBEN D31-D24 D23-D16 D15-D8 D7-D0 BYTE WRITE BYTE WRITE WORD OPERAND WRITE Figure 7-8. Word Operand Write Timing (8-Bit Data Port) 7-14 MC68030 USER’S MANUAL MOTOROLA...
Page 468 Figure 7-14 shows the equivalent operation for a cachable data read cycle. LONG WORD OPERAND DATA BUS WORD MEMORY MC68EC030 MEMORY CONTROL DSACK1 DSACK0 SIZ1 SIZ0 Figure 7-9. Misaligned Long-Word Transfer to Word Port Example MOTOROLA MC68030 USER’S MANUAL 7-15...
Page 469 Bus Operation A31-A2 FC2-FC0 SIZ1 SIZ0 DSACK1 DSACK0 DBEN D31-D24 D23-D16 D15-D8 D7-D0 BYTE WRITE BYTE WRITE WORD WRITE LONG WORD OPERAND WRITE Figure 7-10. Misaligned Long-Word Transfer to Word Port 7-16 MC68030 USER’S MANUAL MOTOROLA...
Page 470 DSACK0 SIZ1 SIZ0 Figure 7-11. Misaligned Cachable Long-Word Transfer from Word Port Example WORD OPERAND DATA BUS MEMORY CONTROL WORD MEMORY MC68030 SIZ1 SIZ0 DSACK1 DSACK0 Figure 7-12. Misaligned Word Transfer to Word Port Example MOTOROLA MC68030 USER’S MANUAL 7-17...
Page 471 Bus Operation A31-A2 FC2-FC0 SIZ1 SIZ0 DSACK1 DSACK0 DBEN D31-D24 D23-D16 D15-D8 D7-D0 WORD WRITE BYTE WRITE WORD OPERAND WRITE TO A1/A0=01 Figure 7-13. Misaligned Word Transfer to Word Port 7-18 MC68030 USER’S MANUAL MOTOROLA...
Page 472 *Instruction prefetches are always two words from a long-word boundary. This table shows that bus cycle throughput is significantly affected by port size and alignment. The MC68030 system designer and programmer should be aware of and account for these effects, particularly in time-critical applications. MOTOROLA MC68030 USER’S MANUAL 7-19...
Page 473 Refer to Section 11 Instruction Execution Timing for a complete description of the cache holding register and pipeline operation. 7-20 MC68030 USER’S MANUAL MOTOROLA...
Page 474 Bus Operation A31-A2 FC2-FC0 SIZ1 SIZ0 DSACK1 DSACK0 DBEN D31-D24 D23-D16 D15-D8 D7-D0 BYTE WRITE 3 - BYTE WRITE LONG WORD OPERAND WRITE Figure 7-16. Misaligned Write Cycles to Long-Word Port MOTOROLA MC68030 USER’S MANUAL 7-21...
Page 475 For cachable read cycles, during which the data is cached, the addressed port must drive all sections of the bus on which it resides. 7-22 MC68030 USER’S MANUAL MOTOROLA...
Page 476 I/O. Figure 7-18 shows a logic diagram for one method for generating byte data enable signals for 16- and 32-bit ports from the size and address encodings and the read/write signal. MOTOROLA MC68030 USER’S MANUAL 7-23...
Page 477 Bus Operation 7.2.5 MC68030 versus MC68020 Dynamic Bus Sizing The MC68030 supports the dynamic bus sizing mechanism of the MC68020 for asynchronous bus cycles (terminated with DSACKx) with two restrictions. First, for a cachable access within the boundaries of an aligned long word, the port size must be consistent throughout the transfer of each long word.
Page 478 (but the bus controller did not begin an external cycle and then abort it) and the second portion in a cache miss, OCS is asserted for the second portion of the operand. MOTOROLA MC68030 USER’S MANUAL 7-25...
Page 479 NOTE: These select lines can be combined with the address decode circuitry or all can be generated within the same programmed array logic unit. Figure 7-18. Byte Data Select Generation for 16- and 32-Bit Ports 7-26 MC68030 USER’S MANUAL MOTOROLA...
Page 480 The BERR and/or HALT signals can be asserted after the DSACKx signal(s) is asserted. BERR and/or HALT must be asserted within the time given as parameter #48, after DSACKx is asserted in any asynchronous system. If this maximum delay time is violated, the processor may exhibit erratic behavior. MOTOROLA MC68030 USER’S MANUAL 7-27...
Page 481 (and/or BERR/HALT) until and throughout the clock edge that negates AS (with the appropriate asynchronous input hold time specified by parameter #47B), no wait states are inserted. The bus cycle runs at its maximum speed (three clocks per cycle) for bus cycles terminated with DSACKx. 7-28 MC68030 USER’S MANUAL MOTOROLA...
Page 482 Again, the exact timing for these subsequent cycles is controlled by the timing of STERM for each of these cycles, and wait cycles can be inserted as necessary. MOTOROLA MC68030 USER’S MANUAL 7-29...
Page 483 In addition, the bus master is responsible for de-skewing the acknowledge and data signals from the slave devices. The following paragraphs define read, write, and read-modify-write cycle operations. An additional paragraph describes burst mode transfers. 7-30 MC68030 USER’S MANUAL MOTOROLA...
Page 484 DBEN inactive to disable the data buffers. SIZ0–SIZ1 become valid, indicating the number of bytes requested to be transferred. CIOUT also becomes valid, indicating the state of the MMU CI bit in the address translation descriptor or in the appropriate TTx register. MOTOROLA MC68030 USER’S MANUAL 7-31...
Page 485 1)SAMPLE CACHE INHIBIT IN (CIIN) 2) LATCH DATA 3) NEGATE AS AND DS 4) NEGATE DBEN TERMINATE CYCLE 1) REMOVE DATA FROM D31-D0 2) NEGATE DSACK START NEXT CYCLE Figure 7-20. Asynchronous Byte Read Cycle Flowchart 7-32 MC68030 USER’S MANUAL MOTOROLA...
Page 486 Bus Operation A31-A2 FC2-FC0 SIZ1 WORD BYTE SIZ0 DSACK1 DSACK0 DBEN D31-D24 D23-D16 D15-D8 D7-D0 WORD READ BYTE READ BYTE READ Figure 7-21. Asynchronous Byte and Word Read Cycles — 32-Bit Port MOTOROLA MC68030 USER’S MANUAL 7-33...
Page 487 BYTE SIZ0 CIOUT DSACK1 DSACK0 DBEN D31-D24 D23-D16 D15-D8 D7-D0 BYTE READ BYTE READ BYTE READ BYTE READ LONG WORD OPERAND READ FROM 8-BIT PORT Figure 7-22. Long-Word Read — 8-Bit Port with CIOUT Asserted MOTOROLA MC68030 USER’S MANUAL 7-35...
Page 488 SIZ0 DSACK1 DSACK0 DBEN D31-D24 D23-D16 D15-D8 D7-D0 WORD READ WORD READ LONG WORD READ FROM 32- BIT PORT LONG WORD OPERAND READ FROM 16-BIT PORT Figure 7-23. Long-Word Read — 16-Bit and 32-Bit Port 7-36 MC68030 USER’S MANUAL MOTOROLA...
Page 489 AS or DS (whichever it detects first). The device must remove its data and negate DSACKx within approximately one clock period after sensing the negation of AS or DS. DSACKx signals that remain asserted beyond this limit may be prematurely detected for the next bus cycle. MOTOROLA MC68030 USER’S MANUAL 7-37...
Page 490 3) ASSERT DATA TRANSFER AND SIZE TERMINATE OUTPUT TRANSFER ACKNOWLEDGE (DSACKx) 1) NEGATE AS AND DS 2) REMOVE DATA FROM D31-D0 TERMINATE CYCLE 3) NEGATE DBEN 1) NEGATE DSACKx START NEXT CYCLE Figure 7-24. Asynchronous Write Cycle Flowchart 7-38 MC68030 USER’S MANUAL MOTOROLA...
Page 491 FC0–FC2. The function codes select the address space for the cycle. The processor drives R/W low for a write cycle. SIZ0–SIZ1 become valid, indicating the number of bytes to be transferred. CIOUT also becomes valid, indicating MOTOROLA MC68030 USER’S MANUAL 7-39...
Page 492 Bus Operation the state of the MMU CI bit in the address translation descriptor or in the appropriate TTx register. 7-40 MC68030 USER’S MANUAL MOTOROLA...
Page 493 Bus Operation A31-A2 FC2-FC0 SIZ1 BYTE WORD SIZ0 DSACK1 DSACK0 DBEN D31-D24 D23-D16 D15-D8 D7-D0 WORD WRITE BYTE WRITE BYTE WRITE Figure 7-26. Asynchronous Byte and Word Write Cycles — 32-Bit Port MOTOROLA MC68030 USER’S MANUAL 7-41...
Page 494 LONG WORD 3-BYTE WORD BYTE SIZ0 DSACK1 DSACK0 DBEN D31-D24 D23-D16 D15-D8 D7-D0 BYTE WRITE BYTE WRITE BYTE WRITE BYTE WRITE LONG WORD OPERAND READ TO 8-BIT PORT Figure 7-27. Long-Word Operand Write — 8-Bit Port 7-42 MC68030 USER’S MANUAL MOTOROLA...
Page 495 LONG WORD WORD SIZ0 DSACK1 DSACK0 DBEN D31-D24 D23-D16 D15-D8 D7-D0 WORD WRITE WORD WRITE LONG WORD WRITE TO 32-BIT PORT LONG WORD OPERAND WRITE TO 16-BIT PORT Figure 7-28. Long-Word Operand Write — 16-Bit Port MOTOROLA MC68030 USER’S MANUAL 7-43...
Page 496 DS (whichever it detects first). The device must negate DSACKx within approximately one clock period after sensing the negation of AS or DS. DSACKx signals that remain asserted beyond this limit may be prematurely detected for the next bus cycle. 7-44 MC68030 USER’S MANUAL MOTOROLA...
Page 497 One-half clock later in S1, the processor asserts AS, indicating that the address on the address bus is valid. The processor asserts DS during S1. In addition, the ECS (and OCS, if asserted) signal is negated during S1. MOTOROLA MC68030 USER’S MANUAL 7-45...
Page 498 2) REMOVE DATA FROM D31-D0 WRITTEN, THEN GO TO 3) NEGATE DBEN TERMINATE CYCLE D ; ELSE GO TO E 1) NEGATE DSACKx UNLOCK BUS 1) NEGATE RMC START NEXT CYCLE Figure 7-29. Asynchronous Read-Modify-Write Cycle Flowchart 7-46 MC68030 USER’S MANUAL MOTOROLA...
Page 499 If a write cycle is required, the R/W signal remains in the read mode until S6 to prevent bus conflicts with the preceding read portion of the cycle; the data bus is not driven until S8. MOTOROLA MC68030 USER’S MANUAL 7-47...
Page 500 A31-A2 FC2-FC0 SIZ1 SIZ0 CIIN CIOUT DSACK1 DSACK0 DBEN D31-D24 D23-D16 D15-D8 D7-D0 BERR HALT INDIVISIBLE CYCLE NEXT CYCLE Figure 7-30. Asynchronous Byte Read-Modify-Write Cycle — 32-Bit Port (TAS Instruction with CIOUT or CIIN Asserted) 7-48 MC68030 USER’S MANUAL MOTOROLA...
Page 501 SIZ0–SIZ1 and A0–A1 select the data bus sections. If it has not already done so, the device asserts DSACKx when it has successfully stored the data. State 10 The processor issues no new control signals during S10. MOTOROLA MC68030 USER’S MANUAL 7-49...
Page 502 DSACKx for three-clock accesses. Figure 7-31 is a flowchart of a synchronous long-word read cycle. Byte and word operations are similar. Figure 7-32 is a functional timing diagram of a synchronous long-word read cycle. 7-50 MC68030 USER’S MANUAL MOTOROLA...
Page 503 (i.e., four long words can be read in), CBREQ is asserted. In addition, the ECS (and OCS, if asserted) signal is negated during S1. MOTOROLA MC68030 USER’S MANUAL 7-51...
Page 504 DBEN may prevent its use. At the beginning of S2, the processor samples the level of STERM. If STERM is recognized, the processor latches the incoming data at the end of S2. If the selected data is not to be cached for the 7-52 MC68030 USER’S MANUAL MOTOROLA...
Page 505 AS and the required assertion of STERM for any two-clock synchronous bus cycle. The system must qualify a memory write with the assertion of AS to ensure that the write is not aborted by internal conditions within the MC68030. MOTOROLA MC68030 USER’S MANUAL 7-53...
Page 506 One-half clock later in S1, the processor asserts AS, indicating that the address on the address bus is valid. The processor also asserts DBEN during S1, which may be used to enable the external data buffers. In addition, the ECS (and OCS, if asserted) signal is negated during S1. 7-54 MC68030 USER’S MANUAL MOTOROLA...
Page 507 If the device does not assert STERM by the rising edge of S2, the processor inserts wait states until it is recognized. The processor asserts DS at the end of S2 if wait states are inserted. For zero-wait-state synchronous write cycles, DS is not asserted. MOTOROLA MC68030 USER’S MANUAL 7-55...
Page 508 Although the operation is synchronous, the burst mode is never used during read-modify-write cycles. Figure 7-35 is a flowchart of the synchronous read-modify-write operation. Timing for the cycle is shown in Figure 7-36. 7-56 MC68030 USER’S MANUAL MOTOROLA...
Page 509 2) REMOVE DATA FROM D31–D0 OPERAND 3) NEGATE DBEN TERMINATE CYCLE WRITTEN, THEN GO TO D : ELSE GO TO E 1) NEGATE STERM UNLOCK BUS 1) NEGATE RMC START NEXT CYCLE Figure 7-35. Synchronous Read-Modify-Write Cycle Flowchart MOTOROLA MC68030 USER’S MANUAL 7-57...
Page 510 The processor places a valid address on A0–A31 and valid function codes on FC0– FC2. The function codes select the address space for the operation. SIZ0–SIZ1 become valid in S0 to indicate the operand size. The processor drives R/W high for a read cycle 7-58 MC68030 USER’S MANUAL MOTOROLA...
Page 511 S2, wait states are inserted after S2, and STERM is sampled on every rising edge thereafter until it is recognized. Once STERM is recognized, data is latched on the next falling edge of the clock (corresponding to the beginning of S3). MOTOROLA MC68030 USER’S MANUAL 7-59...
Page 512 S6, the processor inserts wait states until it is recognized. The processor asserts DS at the end of S6 if wait states are inserted. Note that for zero-wait-state synchronous write cycles, DS is not asserted. 7-60 MC68030 USER’S MANUAL MOTOROLA...
Page 513 However, the MC68030 does not assert CBREQ during the first portion of a misaligned access if the remainder of the access does not correspond to the same cache line. Refer to 6.1.3.1 Single Entry Mode for details. MOTOROLA MC68030 USER’S MANUAL 7-61...
Page 514 An alternate bus master requesting the bus with BR may become bus master at the end of the operation provided BR is asserted early enough to be internally synchronized before another processor cycle begins. Refer to 7.7 Bus Arbitration for more information about bus arbitration. 7-62 MC68030 USER’S MANUAL MOTOROLA...
Page 515 S2, the processor tests the level of STERM. If STERM is recognized, the processor latches the incoming data at the end of S2. For the burst operation to proceed, CBACK must be asserted when STERM is recognized. If the data for the current cycle is MOTOROLA MC68030 USER’S MANUAL 7-63...
Page 516 Figure 7-37. Burst Operation Flowchart — Four Long Words Transferred not to be cached, CIIN must be asserted at the same time as STERM. The assertion of CIIN also has the effect of aborting the burst operation. 7-64 MC68030 USER’S MANUAL MOTOROLA...
Page 517 A2–A0 FC2-FC0 SIZ1–SIZ0 STERM CIIN CIOUT CBREQ CBACK b4–b7 b8–bB bC–bF bC–bF D31–D0 DBEN VALUE OF A3:A2 INCREMENTED BY THE SYSTEM HARDWARE Figure 7-38. Long-Word Operand Request from $07 with Burst Request and Wait Cycle MOTOROLA MC68030 USER’S MANUAL 7-65...
Page 518 2. Continued assertion of CBACK causes data to be placed on D31–D0. 3. Negation of CBACK causes AS to be negated. Figure 7-39. Long-Word Operand Request from $07 with Burst Request — CBACK Negated Early 7-66 MC68030 USER’S MANUAL MOTOROLA...
Page 519 A3–A1 FC2-FC0 SIZ1 SIZ0 STERM CBREQ CBACK b0–b3 b4–b7 b8–bB bC–bF D31–D0 bC–bF DBEN PREVIOUS CACHE BLOCK NEXT CACHE BLOCK - START BURST CYCLE Figure 7-40. Long-Word Operand Request from $0E — Burst Fill Deferred MOTOROLA MC68030 USER’S MANUAL 7-67...
Page 520 CIOUT CBREQ CBACK b4-b7 D31–D0 DBEN BURST MODE ENDS, DATA NOT CACHED VALUE OF A3:A2 INCREMENTED BY THE SYSTEM HARDWARE Figure 7-41. Long-Word Operand Request from $07 with Burst Request — CBACK and CIIN Asserted 7-68 MC68030 USER’S MANUAL MOTOROLA...
Page 521 The same hold times for STERM and data described for S3 apply here. State 6 This state is identical to S4 except that once STERM is recognized, the third long word of data for the burst is latched at the end of S6. MOTOROLA MC68030 USER’S MANUAL 7-69...
Page 522 FC0–FC2 select user and supervisor program and data areas as listed in Table 4-1. The area selected by FC0–FC2=$7 is classified as the CPU space. The interrupt acknowledge, breakpoint acknowledge, and coprocessor communication cycles described in the following sections utilize CPU space. 7-70 MC68030 USER’S MANUAL MOTOROLA...
Page 523 The CPU space type is encoded on A16-A19 during a CPU space operation and indicates the function that the processor is performing. On the MC68030, three of the encodings are implemented as shown in Figure 7-42. All unused values are reserved by Motorola for future additional CPU space types.
Page 524 The responding device places the vector number on the data bus during the interrupt acknowledge cycle. Beyond this, the cycle is terminated normally with either STERM or DSACKx. Figure 7-43 is the flowchart of the interrupt acknowledge cycle. 7-72 MC68030 USER’S MANUAL MOTOROLA...
Page 525 24 ($18). There are seven distinct autovectors that can be used, corresponding to the seven levels of interrupt available with signals IPL0–IPL2. Figure 7-45 shows the timing for an autovector operation. MOTOROLA MC68030 USER’S MANUAL 7-73...
Page 526 DSACK1 DSACK0 DBEN D31-D24 VECTOR # FROM 8-BIT PORT VECTOR # FROM 16-BIT PORT D23-D16 VECTOR # FROM 32-BIT PORT D7-D0 IPL2-IPL0 IPEND INTERRUPT READ CYCLE WRITE STACK ACKNOWLEDGE Figure 7-44. Interrupt Acknowledge Cycle Timing 7-74 MC68030 USER’S MANUAL MOTOROLA...
Page 527 Bus Operation A31-A4 INTERRUPT LEVEL A3-A1 FC2-FC0 SIZ1 SIZ0 DSACK1 DSACK0 DBEN D31-D0 IPL2-IPL0 AVEC INTERRUPT WRITE STACK ACKNOWLEDGE READ CYCLE AUTOVECTORED Figure 7-45. Autovector Operation Timing MOTOROLA MC68030 USER’S MANUAL 7-75...
Page 528 CpID of zero correspond to MMU instructions and are not generated by the MC68030 as a result of the coprocessor interface. These cycles can only be generated by the MOVES instruction. Refer to Section 10 Coprocessor Interface Description for further information. 7-76 MC68030 USER’S MANUAL MOTOROLA...
Page 529 (a user program attempts to access supervisor data, for example) or after the MMU receives a bus error while searching the address table for an address translation description. MOTOROLA MC68030 USER’S MANUAL 7-77...
Page 530 A15-A2 BREAKPOINT NUMBER A1-A0 CPU SPACE FC2-FC0 SIZ1 WORD SIZ0 DSACK1 DSACK0 DBEN D31-D24 D23-D16 D15-D8 D7-D0 BERR HALT BREAKPOINT FETCHED ACKNOWLEDGE INSTRUCTION READ CYCLE INSTRUCTION WORD EXECUTION FETCH Figure 7-47. Breakpoint Acknowledge Cycle Timing 7-78 MC68030 USER’S MANUAL MOTOROLA...
Page 531 Another signal that is used for bus exception control is HALT. This signal can be asserted by an external device for debugging purposes to cause single bus cycle operation or (in combination with BERR) a retry of a bus cycle in error. MOTOROLA MC68030 USER’S MANUAL 7-79...
Page 532 HALT and BERR are asserted in lieu of, at the same time, or before DSACKx (case 5) or after DSACKx (case 6); BERR is negated at the same time or after DSACKx; HALT may be negated at the same time or after BERR. 7-80 MC68030 USER’S MANUAL MOTOROLA...
Page 533 (#61) requirements relative to each rising edge of the processor clock while AS is asserted. Bus error and retry terminations during burst cycles operate as described in 6.1.3.2 Burst Mode Filling, 7.5.1 Bus Errors, and 7.5.2 Retry Operation. MOTOROLA MC68030 USER’S MANUAL 7-81...
Page 534 HALT and BERR are asserted in lieu of, at the same time, or before STERM (case 5) or after STERM (case 6); BERR is negated at the same time or after STERM; HALT may be negated at the same time or after BERR. 7-82 MC68030 USER’S MANUAL MOTOROLA...
Page 535 —Signal was asserted in previous state and remains asserted in this state — —State N+2 not part of bus cycle EXAMPLE A: A system uses a watchdog timer to terminate accesses to an unpopulated address space. The timer asserts BERR after timeout (case 3). MOTOROLA MC68030 USER’S MANUAL 7-83...
Page 536 Should an intervening instruction cause a branch or should a task switch occur, the bus error exception does not occur. 7-84 MC68030 USER’S MANUAL MOTOROLA...
Page 537 BERR must be stable throughout the sample window for the next falling edge of the clock, as defined by specifications #27A and #28A. Figure 7-51 shows the timing for this case. MOTOROLA MC68030 USER’S MANUAL 7-85...
Page 538 BREAKPOINT NUMBER A1-A0 FC2-FC0 CPU SPACE SIZ1 WORD SIZ0 DSACK1 DSACK0 DBEN D31 -D24 D23-D16 D15-D8 D7-D0 BERR HALT BREAKPOINT FETCHED READ CYCLE ACKNOWLEDGE INSTRUCTION BUS ERROR EXECUTION ASSERTED Figure 7-49. Bus Error without DSACKx 7-86 MC68030 USER’S MANUAL MOTOROLA...
Page 539 If the cycle is for a data fetch, the bus error exception is taken immediately. Refer to Section 11 Instruction Execution Timing for more information about pipeline operation. MOTOROLA MC68030 USER’S MANUAL 7-87...
Page 540 Figure 7-53. If BERR is asserted again, the MC68030 then takes an exception. The MC68030 supports late bus errors during a burst fill operation; the timing is the same relative to STERM and the clock as for a late bus error in a normal synchronous cycle. 7-88 MC68030 USER’S MANUAL MOTOROLA...
Page 541 D31–D0 DBEN BERR HALT LATE BERR ENDS BURST; NO EXCEPTION TAKEN 0111 1000 1100 VALUE OF A3:A0 INCREMENTED BY THE SYSTEM HARDWARE Figure 7-52. Long-Word Operand Request — Late BERR on Third Access MOTOROLA MC68030 USER’S MANUAL 7-89...
Page 542 BURST ABORTED RERUN CYCLE TO GET LAST INTERNAL BUS ERROR ASSERTED 3 BYTES OF OPERAND PROCESSING 0111 1000 VALUE OF A3:A0 INCREMENTED BY THE SYSTEM HARDWARE Figure 7-53. Long-Word Operand Request — BERR on Second Access 7-90 MC68030 USER’S MANUAL MOTOROLA...
Page 543 Arbitration Control. The bus error handler software should examine the read-modify-write bit in the special status word (refer to 8.2.1 Special Status Word (SSW)) and take the appropriate action to resolve this type of fault when it occurs. MOTOROLA MC68030 USER’S MANUAL 7-91...
Page 544 Bus Operation A31-A0 FC2-FC0 SIZ1–SIZ0 DSACK1 DSACK0 DATA BUS NOT DRIVEN D31–D0 BERR HALT WRITE CYCLE RETRY SIGNALED HALT RETRY CYCLE Figure 7-54. Asynchronous Late Retry 7-92 MC68030 USER’S MANUAL MOTOROLA...
Page 545 (bus cycle to bus cycle) operation. The HALT signal affects external bus cycles only; thus, a program that resides in the instruction cache and performs no data writes (or reads that miss in the data cache) may continue executing, unaffected by the HALT signal. 7-93 MC68030 USER’S MANUAL MOTOROLA...
Page 546 The single-step operation and the software trace capability allow the system debugger to trace single bus cycles, single instructions, or changes in program flow. These processor capabilities, along with a software debugging package, give complete debugging flexibility. 7-94 MC68030 USER’S MANUAL MOTOROLA...
Page 547 Bus Operation A31-A0 FC2-FC0 SIZ1/SIZ0 DSACK1 DSACK0 DBEN D31-D0 BERR HALT BGACK READ HALT READ (ARBITRATION PERMITTED WHILE THE CONTROLLER IS HALTED) Figure 7-57. Halt Operation Timing 7-95 MC68030 USER’S MANUAL MOTOROLA...
Page 548 A bus cycle that is retried does not constitute a bus error or contribute to a double bus fault. The processor continues to retry the same bus cycle as long as the external hardware requests it. 7-96 MC68030 USER’S MANUAL MOTOROLA...
Page 549 Thus, there is no danger in subsequent instructions using erroneous data from the cache before an external bus error signals an error. A bus synchronization example is given in Figure 7-58. 7-97 MC68030 USER’S MANUAL MOTOROLA...
Page 550 BR signal. When the requesting device receives BG and more than one external device can be bus master, the requesting device should begin whatever arbitration is required. The external device asserts BGACK when it assumes bus mastership and 7-98 MC68030 USER’S MANUAL MOTOROLA...
Page 551 Bus arbitration requests are recognized during normal processing, RESET assertion, HALT assertion, and even when the processor has halted due to a double bus fault. 7-99 MC68030 USER’S MANUAL MOTOROLA...
Page 552 BR is negated. This prevents unnecessary interference with ordinary processing if the arbitration circuitry inadvertently responds to noise or if an external device determines that it no longer requires use of the bus before it has been granted mastership. 7-100 MC68030 USER’S MANUAL MOTOROLA...
Page 553 During a read-modify-write cycle, the processor does not assert BG until the entire operation has completed. RMC is asserted to indicate 7-101 MC68030 USER’S MANUAL MOTOROLA...
Page 554 T. If T is true, the address, data, and control buses are placed in the high-impedance state after the next rising edge following the negation of AS and RMC. All signals are shown in positive logic (active high), regardless of their true active voltage level. 7-102 MC68030 USER’S MANUAL MOTOROLA...
Page 555 3, and negates grant G. The next clock takes the arbiter to state 4, at the upper right, in which grant G remains negated and signal T remains asserted. With acknowledge A asserted, the arbiter remains in state 4 until A is negated or request R is 7-103 MC68030 USER’S MANUAL MOTOROLA...
Page 556 AS must be observed to be negated (high) on two consecutive clock edges before the alternate bus master takes the bus. Waiting for this condition ensures that any current or pending bus activity has completed or has been pre- empted. 7-104 MC68030 USER’S MANUAL MOTOROLA...
Page 557 RESET negates, all control signals are driven to their inactive state, the data bus is in read mode, and the address bus is driven. After this, the first bus cycle for reset exception processing begins. 7-105 MC68030 USER’S MANUAL MOTOROLA...
Page 558 RESET should be asserted for at least 520 clock periods to ensure that the processor resets. Asserting RESET for 10 clock periods is sufficient for resetting the processor logic; the additional clock periods prevent a reset instruction from overlapping the external RESET signal. 7-106 MC68030 USER’S MANUAL MOTOROLA...
Page 559 Figure 7- 65 shows the timing information for the reset instruction. 7-107 MC68030 USER’S MANUAL MOTOROLA...
Page 560 Bus Operation A31-A0 FC2-FC0 SIZ1-SIZ0 DSACK1 DSACK0 DBEN D31-D0 HALT RESET RESUME NORMAL RESET INTERNAL READ OPERATION 512 CLOCKS Figure 7-65. Processor-Generated Reset Operation 7-108 MC68030 USER’S MANUAL MOTOROLA...
Page 561 (a read from the CPU address space type $F; see Figures 7-45 and 7-46) to obtain the vector number. For coprocessor-detected exceptions, the vector number is included in the coprocessor exception primitive response. MOTOROLA MC68030 USER’S MANUAL...
Page 562 Reset Initial Program Counter — Bus Error Address Error Illegal Instruction Zero Divide CHK, CHK2 Instruction cpTRAPcc, TRAPcc, TRAPV Instructions Privilege Violation Trace Line 1010 Emulator Line 1111 Emulator (Unassigned, Reserved) — Coprocessor Protocol Violation Format Error Uninitialized Interrupt MC68030 USER’S MANUAL MOTOROLA...
Page 563 SP = Supervisor Program Space SD = Supervisor Data Space As shown in Table 8-1, the first 64 vectors are defined by Motorola and 192 vectors are reserved for interrupt vectors defined by the user. However, external devices may use vectors reserved for internal purposes at the discretion of the system designer.
Page 564 Exception processing to begin for: • reset OR • bus error OR • address error OR • spurious interrupt OR • autovectored interrupt OR • F-line instruction (no coprocessor responded) Continuously Processor halted due to double bus fault. MC68030 USER’S MANUAL MOTOROLA...
Page 565 After the initial instruction prefetches, program execution begins at the address in the program counter. The reset exception does not flush the address translation cache (ATC), nor does it save the value of either the program counter or the status register. MOTOROLA MC68030 USER’S MANUAL...
Page 566 OTHERWISE PC (VECTOR #1) (DOUBLE BUS FAULT) ASSERT STATUS PREFETCH 3 WORDS CONTINUOUSLY EXIT OTHERWISE BUS ERROR OR ADDRESS ERROR BEGIN INSTRUCTION EXECUTION (DOUBLE BUS FAULT) EXIT ASSERT STATUS CONTINUOUSLY EXIT Figure 8-1. Reset Operation Flowchart MC68030 USER’S MANUAL MOTOROLA...
Page 567 BERR signal during a bus cycle used to access the translation tables. A miss in the ATC causes the processor to automatically initiate a table search but does not cause a bus error exception unless one of the specific conditions mentioned above is encountered. MOTOROLA MC68030 USER’S MANUAL...
Page 568 3 and the vector offset in the stack frame refers to the address error vector. Either a short or long bus fault stack frame may be generated. If an address error occurs during the exception processing for a bus error, address error, or reset, a double bus fault occurs. MC68030 USER’S MANUAL MOTOROLA...
Page 569 MC68030 instruction or is a MOVEC instruction with an undefined register specification field in the first extension word. An illegal instruction exception corresponds to vector number 4 and occurs when the processor attempts to execute an illegal instruction. MOTOROLA MC68030 USER’S MANUAL...
Page 570 (F-line opcode) exception. The system can emulate the functions of the coprocessor with an F-line exception handler. Refer to Section 10 Coprocessor Interface Description for more details. 8-10 MC68030 USER’S MANUAL MOTOROLA...
Page 571 An attempt to execute one of the privileged instructions while at the user privilege level causes a privilege violation exception. Also, a privilege violation exception occurs if a coprocessor requests a privilege check and the processor is at the user level. MOTOROLA MC68030 USER’S MANUAL 8-11...
Page 572 (i.e., a jump, branch, etc.). Setting the T1 bit and clearing the T0 bit causes the execution of all instructions to force trace exceptions. Table 8-3 shows the trace mode selected by each combination of T1 and T0. 8-12 MC68030 USER’S MANUAL MOTOROLA...
Page 573 The saved value of the program counter is the logical address of the next instruction to be executed. Instruction execution resumes after the required prefetches from the address in the trace exception vector. MOTOROLA MC68030 USER’S MANUAL 8-13...
Page 574 When a peripheral device requires the services of the MC68030 or is ready to send information that the processor requires, it may signal the processor to take an interrupt exception. The interrupt exception transfers control to a routine that responds appropriately. 8-14 MC68030 USER’S MANUAL MOTOROLA...
Page 575 Figure 8-2 is a flowchart of the procedure for making an interrupt pending. RESET SAMPLE AND SYNCH IPL2-IPL0 (COMPARE INTERRUPT LEVEL WITH STATUS REGISTER MASK) > OTHERWISE INTERRUPT LEVEL I2-I0, OR TRANSITION ON LEVEL 7 ASSERT IPEND Figure 8-2. Interrupt Pending Procedure MOTOROLA MC68030 USER’S MANUAL 8-15...
Page 576 (with the MOVE to SR or RTE instruction, for example). As shown in Figure 8-3 for level 6 interrupt request level and mask level, this is the case for all interrupt levels. 8-16 MC68030 USER’S MANUAL MOTOROLA...
Page 577 Figure 8-4 shows the assertion of IPEND relative to the assertion of an interrupt level on the IPL lines. IPEND signals to external devices that an interrupt exception will be taken at an upcoming instruction boundary (following any higher priority exception). MOTOROLA MC68030 USER’S MANUAL 8-17...
Page 578 If no higher priority interrupt has been synchronized, the IPEND signal is negated during state 0 (S0) of an interrupt acknowledge cycle (refer to 7.4.1.1 Interrupt Acknowledge Cycle — Terminated Normally ), and the IPLx signals for the interrupt being acknowledged can be negated at this time. 8-18 MC68030 USER’S MANUAL MOTOROLA...
Page 579 M = 0 VECTOR TABLE ENTRY TEMP PREFETCH 3 WORDS BEGIN EXECUTION OF THE INTERRUPT END OF EXCEPTION PROCESSING HANDLER ROUTINE OR PROCESS A FOR THE INTERRUPT HIGHER PRIORITY EXCEPTION Figure 8-5. Interrupt Exception Processing Flowchart MOTOROLA MC68030 USER’S MANUAL 8-19...
Page 580 24. Refer to 7.4.1 Interrupt Acknowledge Bus Cycles for complete interrupt bus cycle information. 8-20 MC68030 USER’S MANUAL MOTOROLA...
Page 581 The exception is a post-instruction exception; it is processed after the instruction completes. The processor generates exception vector number 56 when an MMU configuration exception occurs. Refer to Section 9 Memory Management Unit for a description of the valid configurations for the MMU registers. MOTOROLA MC68030 USER’S MANUAL 8-21...
Page 582 For the MC68000 and MC68008, this can be done by inserting an illegal instruction at the breakpoint and detecting the illegal instruction exception from its vector location. However, since the vector base register on the MC68010, MC68020, and MC68030 allows arbitrary relocation of exception vectors, the exception address cannot reliably identify a breakpoint.
Page 583 However, most exceptions cannot occur during exception processing, and very few combinations of the exceptions shown in Table 8-5 can be pending simultaneously. MOTOROLA MC68030 USER’S MANUAL 8-23...
Page 584 Once the exception handler has completed execution, the processor must return to the system context prior to the exception (if possible). The RTE instruction returns from the handler to the previous system context for any exception. 8-24 MC68030 USER’S MANUAL MOTOROLA...
Page 585 BERR signal causes the processor to enter the halted state with the continuous assertion of the STATUS signal. Refer to 8.2 Bus Fault Recovery for a description of the processing that occurs after the frame is read into the internal registers. MOTOROLA MC68030 USER’S MANUAL 8-25...
Page 586 In a multiprocessor system, the faulty frame can be left to be used by another processor of a different type (e.g., an MC68010, MC68020, or a future M68000 processor) when appropriate. 8-26 MC68030 USER’S MANUAL...
Page 587 SP+$24 contains the address of the stage B word; the address of the stage C word is the address of the stage B word minus two. Address error faults occur only for instruction stream accesses, and the exceptions are taken before the bus cycles are attempted. MOTOROLA MC68030 USER’S MANUAL 8-27...
Page 588 8-28 MC68030 USER’S MANUAL MOTOROLA...
Page 589 In addition, the handler must clear the rerun bit associated with the stage that it has corrected. The handler should not change the fault bits FB and FC. MOTOROLA MC68030 USER’S MANUAL 8-29...
Page 590 Address error faults must be repaired in software. Address error faults can be distinguished from bus error faults by the value in the vector offset field of the format word. 8-30 MC68030 USER’S MANUAL MOTOROLA...
Page 591 R/W signal. Otherwise, the potential for partially destroying system pointers with CAS and CAS2 instructions exists since one portion of the write operation could take place and the remainder be aborted by a bus error. MOTOROLA MC68030 USER’S MANUAL 8-31...
Page 592 For compatibility with future devices, the software should be able to handle any type of stack frame for any type of exception. Table 8-6 summarizes the stack frames defined for the M68000 Family. 8-32 MC68030 USER’S MANUAL MOTOROLA...
Page 593 Exception Processing Exception Stack Frames (Sheet 1 of 2). MOTOROLA MC68030 USER’S MANUAL 8-33...
Page 594 Exception Processing Table 8-5. Exception Stack Frames (Sheet 2 of 2). 8-34 MC68030 USER’S MANUAL MOTOROLA...
Page 595 • Eight Page Sizes: 256, 512, 1K, 2K, 4K, 8K, 16K and 32K Bytes • Separate User and Supervisor Translation Table Trees Are Supported • Two Independent Blocks Can Be Defined as Transparent (Untranslated) • Multiple Levels of Translation Tables MOTOROLA MC68030 USER’S MANUAL...
Page 596 Each transparent translation register can define a block of logical addresses that are used as physical addresses (without translation). The MMU status register contains accumulated status information from a translation performed as a part of a PTEST instruction. MC68030 USER’S MANUAL MOTOROLA...
Page 597 Memory Management Unit Figure 9-1. MMU Block Diagram MOTOROLA MC68030 USER’S MANUAL...
Page 598 The TC register specifies how many bits of the logical address are used as the index for each level of the lookup (as many as 15 bits can be used at a given level). MC68030 USER’S MANUAL MOTOROLA...
Page 599 CI - CACHE INHIBIT R/W - READ/WRITE RWM - READ WRITE MASK FC BASE - FUNCTION CODE VALUE FOR BLOCK FC MASK - FUNCTION CODE BITS TO BE IGNORED FIG 9-3 Figure 9-3. Translation Table Tree MOTOROLA MC68030 USER’S MANUAL...
Page 600 A two-level page task is shown. The 32-bit logical address space is divided into 4096 segments of 1024 bytes each. Figure 9-5 shows a possible layout of this example translation tree in memory. MC68030 USER’S MANUAL MOTOROLA...
Page 601 Memory Management Unit AC - ACCESS CONTROLLED FIG 9-4 Figure 9-4. Example Translation Table Tree MOTOROLA MC68030 USER’S MANUAL...
Page 602 (or represents) a page descriptor. Figure 9-6 shows how the TIx fields of the TC register apply to a function code and logical address. (UNABLE TO LOCATE ART) Figure 9-6. Derivation of Table Index Fields MC68030 USER’S MANUAL MOTOROLA...
Page 603 (Refer to 9.5.3.1 Early Termination and Contiguous Memory ). 1.NOTE 1: If any of these ﬁelds are zero, the remaining ﬁelds are ignored. MOTOROLA MC68030 USER’S MANUAL...
Page 604 In these two cases, the exception routine can either restore the page from disk or add to the translation table. 9-10 MC68030 USER’S MANUAL MOTOROLA...
Page 605 If an access hits in the ATC but a bus error was detected during the table search that created the ATC entry, the memory access is aborted, and a bus error exception is taken. MOTOROLA MC68030 USER’S MANUAL 9-11...
Page 606 Note that the assertion of MMUDIS does not affect the operation of the transparent translation registers. 9-12 MC68030 USER’S MANUAL MOTOROLA...
Page 607 Otherwise, neither the read nor write portions of read-modify-write operations are mapped transparently with the TTx registers, regardless of the function code and address bits for the individual cycles within a read-modify-write operation. MOTOROLA MC68030 USER’S MANUAL 9-13...
Page 608 The MC68030 is organized such that the translation time of the ATC is always completely overlapped by other operations; thus, no performance penalty is associated with ATC searches. The address translation occurs in parallel with on-chip instruction and data cache accesses before an external bus cycle begins. 9-14 MC68030 USER’S MANUAL MOTOROLA...
Page 609 256 bytes. For larger page sizes, the appropriate number of least signifi- cant bits of this field are ignored. MOTOROLA MC68030 USER’S MANUAL 9-15...
Page 610 M bit in both the ATC and the page descriptor in the translation tables even when a previous read operation to the page had created an entry for that page in the ATC with the M bit clear. 9-16 MC68030 USER’S MANUAL MOTOROLA...
Page 611 (in the bottom level of the translation tree). A page descriptor at a higher level is an early termination page descriptor. A table search ends when a page descriptor of either type is en- countered. MOTOROLA MC68030 USER’S MANUAL 9-17...
Page 612 This bit is set to inhibit caching of items within this page by the on-chip instruction and data caches and, also, to cause the assertion of the CIOUT signal by the MC68030 for bus cy- cles accessing items within this page. 9-18 MC68030 USER’S MANUAL MOTOROLA...
Page 613 TABLE ADDRESS This 28-bit field contains the physical base address of a table of descriptors. The low-or- der bits of the address are supplied by the logical address. MOTOROLA MC68030 USER’S MANUAL 9-19...
Page 614 RESERVED Descriptor fields designated by a one or a zero are reserved by Motorola for future defini- tion. These bits should be consistently written as either a one or a zero as appropriate. In the root pointers, these bits are not alterable. In memory-resident descriptors, the values in these fields are neither checked nor altered by the MC68030.
Page 615 Figure 9-13 shows the format of the long-format early termination page descriptor. The LIMIT field of the long-format descriptor provides a means of limiting the number of pages to which the descriptor applies. (UNABLE TO LOCATE ART) Figure 9-13. Long-Format Early Termination Page Descriptor MOTOROLA MC68030 USER’S MANUAL 9-21...
Page 616 For example, the disk address of disk- resident tables or pages can be stored in this field. Figure 9-15 shows the format of a short- format invalid descriptor. (UNABLE TO LOCATE ART) Figure 9-15. Short-Format Invalid Descriptor 9-22 MC68030 USER’S MANUAL MOTOROLA...
Page 617 The field descriptions in 9.5.1.1 Descriptor Field Definitions apply to the corresponding fields of this descriptor. Figure 9-17 shows the format of a short- format indirect descriptor. (UNABLE TO LOCATE ART) Figure 9-17. Short-Format Indirect Descriptor MOTOROLA MC68030 USER’S MANUAL 9-23...
Page 618 SRP register is selected only when SRE and FC2 are both set. Otherwise, the translation table with its root defined by the CRP register is selected. A simplified flowchart of the table search procedure is shown in Figure 9-19. 9-24 MC68030 USER’S MANUAL MOTOROLA...
Page 619 The page descriptor contains the physical address and other information needed for the ATC entry; the MC68030 creates the ATC entry and retries the original bus access. Figure 9-20 shows a table search using the function code and all four TIx fields. MOTOROLA MC68030 USER’S MANUAL 9-25...
Page 620 A limit violation or a bus error due to a system malfunction may result in an error message and termination of the task. 9-26 MC68030 USER’S MANUAL MOTOROLA...
Page 621 (with n unused bits set to zero) to a contiguous region in the physical address space starting at the page frame base address PS+n with a size of 2 bytes. MOTOROLA MC68030 USER’S MANUAL 9-27...
Page 622 The processor then fetches the page descriptor of the indicated format from this address and uses the page address field of the page descriptor as the physical mapping for the logical address. 9-28 MC68030 USER’S MANUAL MOTOROLA...
Page 623 Memory Management Unit (UNABLE TO LOCATE ART) Figure 9-21. Example Translation Tree Using Contiguous Memory MOTOROLA MC68030 USER’S MANUAL 9-29...
Page 624 . . .etc.) and possibly the disk address for nonresident tables. Figure 9-24 shows an address translation table in which only a single page table (table n) is resident and all other page tables are not resident. 9-30 MC68030 USER’S MANUAL MOTOROLA...
Page 625 Memory Management Unit (UNABLE TO LOCATE ART) Figure 9-23. Example Translation Tree Using Shared Tables MOTOROLA MC68030 USER’S MANUAL 9-31...
Page 626 9.5.4 Detail of Table Search Operations The table search operations described in this section are shown in detail in Figures 9-25-9- 9-32 MC68030 USER’S MANUAL MOTOROLA...
Page 627 Memory Management Unit (UNABLE TO LOCATE ART) Figure 9-25. Detailed Flowchart of MMU Table Search Operation MOTOROLA MC68030 USER’S MANUAL 9-33...
Page 628 Memory Management Unit (UNABLE TO LOCATE ART) Figure 9-26. Table Search Initialization Flowchart (UNABLE TO LOCATE ART) Figure 9-27. ATC Entry Creation Flowchart 9-34 MC68030 USER’S MANUAL MOTOROLA...
Page 629 (WP) bit, which can be set to provide write protection at any level. Each long-format table and page descriptor also contains a supervisor-only (S) bit, which can limit access to programs operating at the supervisor privilege level. MOTOROLA MC68030 USER’S MANUAL 9-35...
Page 630 Figure 9-31 shows a translation tree using function code lookup, and Figure 9-32 shows translation trees for two tasks that share common supervisor spaces. (UNABLE TO LOCATE ART) Figure 9-30. Logical Address Map Using Function Code Lookup 9-36 MC68030 USER’S MANUAL MOTOROLA...
Page 631 Memory Management Unit (UNABLE TO LOCATE ART) Figure 9-31. Example Translation Tree Using Function Code Lookup MOTOROLA MC68030 USER’S MANUAL 9-37...
Page 632 Figure 9-33 shows a memory map of the logical address space organized to use S and WP bits for protection. Figure 9-34 shows an example translation tree for this technique. 9-38 MC68030 USER’S MANUAL MOTOROLA...
Page 633 Memory Management Unit (UNABLE TO LOCATE ART) Figure 9-33. Exmple Logical Address Map with Shared Supervisor and User Address Spaces MOTOROLA MC68030 USER’S MANUAL 9-39...
Page 634 Memory Management Unit (UNABLE TO LOCATE ART) Figure 9-34. Exmple Translation Tree Using S and WP Bits to Set Protection 9-40 MC68030 USER’S MANUAL MOTOROLA...
Page 635 9.6 MC68030 AND MC68851 MMU DIFFERENCES The MC68851 paged memory management unit provides memory management for the MC68020 as a coprocessor. The on-chip MMU of the MC68030 provides many of the features of the MC68020/MC68851 combination. The following functions of the MC68851 are not available in the MC68030 MMU: •...
Page 636 Specifies that the value contained in the limit field is to be used as the unsigned lower limit of indexes into the translation tables when this bit is set. When this bit is cleared, the limit field is the unsigned upper limit of the translation table indexes. 9-42 MC68030 USER’S MANUAL MOTOROLA...
Page 637 The table address field can contain zero (for zero offset). Unused Bits 3-0 of the root pointer are not used and are ignored when written. All other unused bits must always be zeros. MOTOROLA MC68030 USER’S MANUAL 9-43...
Page 638 When the SRP is disabled, both user and supervisor accesses use the translation table defined by the CRP. When the SRP is enabled, user accesses use the CRP, and super- visor accesses use the SRP. 9-44 MC68030 USER’S MANUAL MOTOROLA...
Page 639 TIA. When function code lookup is enabled, the first table of the translation table structure is indexed by func- tion code. In this case, the limit field of CRP or SRP is ignored. MOTOROLA MC68030 USER’S MANUAL 9-45...
Page 640 1110 — 16K bytes 1111 — 32K bytes All other bit combinations are reserved by Motorola for future use; an attempt to load oth- er values into this field of the TC register causes an MMU configuration exception. Initial Shift (IS) This 4-bit field contains the number of high-order bits of the logical address that are ig- nored during table search operations.
Page 641 This bit defines the type of access that is transparently translated (for a matching ad- dress): 0 — Write accesses transparent 1 — Read accesses transparent Read/Write Mask (RWM) This bit masks the R/W field: 0 — R/W field used 1 — R/W field ignored MOTOROLA MC68030 USER’S MANUAL 9-47...
Page 642 FC BASE field to be ignored. LOGICAL ADDRESS BASE This 8-bit field is compared with address bits A31-A24. Addresses that match in this comparison (and are otherwise eligible) are transparently translated. 9-48 MC68030 USER’S MANUAL MOTOROLA...
Page 643 ATC (PTEST with level 0) or the translation tables (PTEST with levels of 1-7) to determine status information about the translation of a specified logical address. The MMUSR is shown in Figure 9-38. (UNABLE TO LOCATE ART) Figure 9-38. MMU Status Register (MMUSR) Format MOTOROLA MC68030 USER’S MANUAL 9-49...
Page 644 T bit is set, all remaining MMUSR bits are undefined. Number of Levels (N) This 3-bit field is cleared to zero. This 3-bit field contains the actual number of tables accessed during the search. 9-50 MC68030 USER’S MANUAL MOTOROLA...
Page 645 Figure 9-39 shows the flow for a PTEST instruction for the ATC (level 0), and Figure 9-40 shows the flow for a PTEST instruction that accesses an address translation tree (levels 1-7). MOTOROLA MC68030 USER’S MANUAL 9-51...
Page 646 A PMOVE instruction that loads either the CRP or the SRP causes an MMU configuration exception if the new value of the DT field is zero (invalid). In this case, the register is loaded with the new value before the exception is taken. 9-52 MC68030 USER’S MANUAL MOTOROLA...
Page 647 MMU registers. The operating system uses the PMOVE instruction to control and monitor MMU operation by manipulating and reading these registers. Optionally, a PMOVE instruction flushes the ATC when it loads a value into the TC, SRP, CRP, TT0, or TT1 register. MOTOROLA MC68030 USER’S MANUAL 9-53...
Page 648 If execution of a unimplemented F-line instruction with CpID=0 is attempted in the user mode, the MC68030 takes a privilege violation exception. F-line instructions with a CpID other than zero are executed as coprocessor instructions by the MC68030. 9-54 MC68030 USER’S MANUAL MOTOROLA...
Page 649 A single translation table maps all supervisor accesses without maintaining a large number of supervisor pointers in the translation tables for each task, resulting in reduced bus activity for table searches. MOTOROLA MC68030 USER’S MANUAL 9-55...
Page 650 This scheme might be ideal for real-time systems that do not require more complexity in memory management facilities. 9-56 MC68030 USER’S MANUAL MOTOROLA...
Page 651 The advantages of this implementation are the maximum availability of the virtual space and a complete logical separation of addresses. Virtual machine implementations require maximum availability of virtual space. The disadvantages are the more complex table management and the more restrictive accesses to other address spaces. MOTOROLA MC68030 USER’S MANUAL 9-57...
Page 652 Systems with smaller page sizes have a higher frequency of page faults requiring more table search time and paging I/O. With the flexibility of the MC68030 MMU, the designer has enough choices to optimize table structure design and page size. 9-58 MC68030 USER’S MANUAL MOTOROLA...
Page 653 (i.e., out-of-bounds) addresses. Using the full 32-bit address and reducing the table size with invalid descriptors and limited pointer and page table sizes prevents this problem. MOTOROLA MC68030 USER’S MANUAL 9-59...
Page 654 The MC68030 creates multiple ATC entries (one for each page) for the range of virtual addresses represented by the early termination descriptor as the pages are accessed. 9-60 MC68030 USER’S MANUAL MOTOROLA...
Page 655 Pages that do not have the M (modified) bit set should be taken first, since they do not need to be copied to the paging device (the existing image remains valid). MOTOROLA MC68030 USER’S MANUAL 9-61...
Page 656 However, preliminary software model simulations show that 8K-byte pages provide optimum performance for this type of processing. 9-62 MC68030 USER’S MANUAL MOTOROLA...
Page 657 96 bytes. A task that requires more than 16 Mbytes uses more than one valid entry in the higher level table. MOTOROLA MC68030 USER’S MANUAL 9-63...
Page 658 It must know the total amount of virtual memory space, how much is allocated, and which areas are available to be assigned to tasks. The virtual memory map looks like this: (UNABLE TO LOCATE ART) Virtual addresses for this virtual memory are subdivided: (UNABLE TO LOCATE ART) 9-64 MC68030 USER’S MANUAL MOTOROLA...
Page 659 All the operating system has to do when creating the address table for a new task is to set the first upper level table entry to point to the common page table of the supervisor. MOTOROLA MC68030 USER’S MANUAL 9-65...
Page 660 SwapInPage, reads in the image. The input parameter for this routine is the invalid descriptor, which contains the disk address of the page image. Before returning, SwapInPage replaces the invalid descriptor with a valid page descriptor that contains the page address. The page is now ready for use. 9-66 MC68030 USER’S MANUAL MOTOROLA...
Page 661 By convention, the first entry maps the supervisor address space and has supervisor protection. The routine never modifies this first entry. The 31 entries after the first are available to be allocated as user address space. MOTOROLA MC68030 USER’S MANUAL 9-67...
Page 662 When the PTEST instruction does not find any error, the bus error was most likely a malfunction (for example, a transient memory failure). The operating system must respond appropriately. 9-68 MC68030 USER’S MANUAL MOTOROLA...
Page 663 However, the example operating system does not consider the type of request, but assigns a physical page frame to the page and writes the page descriptor to the page table. Some systems clear virgin pages to zero. MOTOROLA MC68030 USER’S MANUAL 9-69...
Page 664 Page stealing software can involve many dynamics of the system. It can consider task priority, I/O activity, working-set determinations, the number of executing tasks, a thrashing level, and other factors. 9-70 MC68030 USER’S MANUAL MOTOROLA...
Page 665 The code is further simplified by omitting the function code value and the read/write status, which do not affect the basic logic of the program. (UNABLE TO LOCATE ART) (UNABLE TO LOCATE ART) (UNABLE TO LOCATE ART) 9-71 MC68030 USER’S MANUAL MOTOROLA...
Page 666 Memory Management Unit 9-72 MC68030 USER’S MANUAL MOTOROLA...
Page 667 MC68030. The designer of a system that uses one or more Motorola coprocessors (the MC68881 or MC68882 floating-point coprocessor, for example) does not require a detailed knowledge of the M68000 coprocessor interface.
Page 668 If the coprocessor uses the synchronous bus interface all coprocessor signals and data must be synchronized with the main processor clock. Both the MC68881 and MC68882 floating-point coprocessors use the asynchronous bus handshake protocol. 10-2 MC68030 USER’S MANUAL MOTOROLA...
Page 669 The MC68882 coprocessor offers concurrent instruction execution while the MC68881 coprocessor does not. However, the MC68030 can execute instructions concurrently with coprocessor instruction execution in the MC68881. MOTOROLA MC68030 USER’S MANUAL 10-3...
Page 670 The MC68030 never generates coprocessor interface bus cycles with the CpID equal to zero (except via the MOVES instruction). CpID codes of 001-101 are reserved for current and future Motorola coprocessors and CpID codes of 110-111 are reserved for user-defined coprocessors. The Motorola CpID code that is currently defined is 001 for the MC68881 or MC68882 floating-point coprocessor.
Page 671 CIR using the coprocessor interface. The bus interface circuitry of a coprocessor operating as a bus slave is not as complex as that of a device operating as a bus master. MOTOROLA MC68030 USER’S MANUAL 10-5...
Page 672 MC68030 address, data, and control signal timing. The MC68030 timing information for read and write cycles is illustrated in Figures 13-5-13-8 on foldout pages in the back of this manual. The MC68030 never requests a burst operation 10-6 MC68030 USER’S MANUAL MOTOROLA...
Page 673 CPU address space. Signals A0–A4 of the MC68030 address bus select the CIR being accessed. The register map for the M68000 coprocessor interface is shown in Figure 10-5. The individual registers are described in detail in 10.3 Coprocessor Interface Register Set . MOTOROLA MC68030 USER’S MANUAL 10-7...
Page 674 INTERFACE REGISTER SET ADDRESS SPACE FOR 2201F COPROCESSOR WITH CpID = 1 RESERVED 24000 2E000 INTERFACE REGISTER SET ADDRESS SPACE FOR 2E01F COPROCESSOR WITH CpID = 7 RESERVED Figure 10-4. Coprocessor Address Map in MC68030 CPU Space 10-8 MC68030 USER’S MANUAL MOTOROLA...
Page 675 M68000 coprocessor interface to indicate its status to the main processor. 10.2.1 Coprocessor General Instructions The general coprocessor instruction category contains data processing instructions and other general-purpose instructions for a given coprocessor. MOTOROLA MC68030 USER’S MANUAL 10-9...
Page 676 0-5 can have any value (don't cares). The second word of the general-type instruction is the coprocessor command word. The main processor writes this command word to the command CIR to initiate execution of the instruction by the coprocessor. 10-10 MC68030 USER’S MANUAL MOTOROLA...
Page 677 The implementation of instructions in the conditional category promotes efficient use of both the main processor's and the coprocessor's hardware. The condition specified for the instruction is related to the coprocessor operation and is, therefore, evaluated by the MOTOROLA MC68030 USER’S MANUAL 10-11...
Page 678 The main processor performs the change of flow, the setting of a byte, or the TRAP operation, since its architecture explicitly implements these operations for its instruction set. 10-12 MC68030 USER’S MANUAL MOTOROLA...
Page 679 The value in bits [8:6] identifies either the word or the long- word displacement format of the branch instruction, which is specified by the cpBcc.W or cpBcc.L mnemonic, respectively. MOTOROLA MC68030 USER’S MANUAL 10-13...
Page 680 The final word(s) of the cpBcc instruction format contains the displacement used by the main processor to calculate the destination address when the branch is taken. 10-14 MC68030 USER’S MANUAL MOTOROLA...
Page 681 10.2.2.2.1 Format. Figure 10-11 shows the format of the set on coprocessor condition instruction, denoted by the cpScc mnemonic. CpID EFFECTIVE ADDRESS CONDITION SELECTOR OPTIONAL COPROCESSOR-DEFINED WORDS OPTIONAL EFFECTIVE ADDRESS EXTENSION WORDS(0-5WORDS) Figure 10-11. Set On Coprocessor Condition (cpScc) MOTOROLA MC68030 USER’S MANUAL 10-15...
Page 682 The second word of the cpScc instruction format contains the coprocessor condition selector in bits [0-5]. Bits [6-15] of this word are reserved by Motorola and should be zero to ensure compatibility with future M68000 products. This word is written to the condition CIR to initiate the cpScc instruction.
Page 683 The last word of the instruction contains the displacement for the cpDBcc instruction. This displacement is a twos-complement 16-bit value that is sign-extended to long-word size when it is used in a destination address calculation. MOTOROLA MC68030 USER’S MANUAL 10-17...
Page 684 10.2.2.4.1 Format. Figure 10-13 shows the format of the trap on coprocessor condition instruction, denoted by the cpTRAPcc mnemonic. CpID OPMODE (RESERVED) CONDITION SELECTOR OPTIONAL COPRCESSOR-DEFINED EXTENSION WORDS OPTIONAL WORD OR LONG-WORD OPERAND Figure 10-13. Trap On Coprocessor Condition (cpTRAPcc) 10-18 MC68030 USER’S MANUAL MOTOROLA...
Page 685 (refer to 10.5.2.4 cpTRAPcc Instruction Traps). If the coprocessor returns the false condition indicator, the main processor executes the next instruction in the instruction stream. MOTOROLA MC68030 USER’S MANUAL 10-19...
Page 686 During execution of the cpRESTORE instruction, the MC68030 reads the format word and long words in the state frame from ascending addresses, beginning with the effective address specified in the instruction operation word. 10-20 MC68030 USER’S MANUAL MOTOROLA...
Page 687 If cpGEN instructions are provided to save the program visible state of the coprocessor, the cpSAVE and cpRESTORE instructions should only transfer the program invisible state information to minimize interrupt latency during a save or restore operation. MOTOROLA MC68030 USER’S MANUAL 10-21...
Page 688 Thus, an empty/reset state frame consists only of the format word and the following reserved word in memory (refer to Figure 10-14). 10-22 MC68030 USER’S MANUAL MOTOROLA...
Page 689 CIR and initiates format error exception processing. The two least significant bits of the abort mask are 01; the fourteen most significant bits are undefined. MOTOROLA MC68030 USER’S MANUAL 10-23...
Page 690 [9-11] and an M68000 effective address code in bits [0-5]. The effective address encoded in the cpSAVE instruction is the address at which the state frame associated with the current context of the coprocessor is saved in memory. 10-24 MC68030 USER’S MANUAL MOTOROLA...
Page 691 CIR, it returns a “not ready'“ format code. The main processor services any pending interrupts and then reads the save CIR again. After placing the not ready format code in the save CIR, the coprocessor should either suspend or complete the instruction it is currently executing. MOTOROLA MC68030 USER’S MANUAL 10-25...
Page 692 During the execution of a cpRESTORE instruction, the coprocessor can communicate status information to the main processor by placing format codes in the restore CIR. 10.2.3.4.1 Format. Figure 10-17 shows the format of the cpRESTORE instruction. 10-26 MC68030 USER’S MANUAL MOTOROLA...
Page 693 [0-5] of the operation word. All memory addressing modes except the predecrement addressing mode are valid. Invalid effective address encodings cause the MC68030 to initiate F-line emulator exception processing (refer to 10.5.2.2 F-Line Emulator Exceptions). MOTOROLA MC68030 USER’S MANUAL 10-27...
Page 694 The complete register model must be implemented if the system uses all of the coprocessor response primitives defined for the M68000 coprocessor interface. The following paragraphs contain detailed descriptions of the registers. 10-28 MC68030 USER’S MANUAL MOTOROLA...
Page 695 CIR to receive the coprocessor response primitives during the execution of instructions in the general and conditional instruction categories. The offset from the base address of the CIR set for the response CIR is $00. Refer to 10.4 Coprocessor Response Primitives. MOTOROLA MC68030 USER’S MANUAL 10-29...
Page 696 CIR to initiate execution of the cpSAVE instruction by the coprocessor. The offset from the base address of the CIR set for the save CIR is $04. Refer to 10.2.3.2 Coprocessor Format Words. 10-30 MC68030 USER’S MANUAL MOTOROLA...
Page 697 16-bit condition CIR. The offset from the base address of the CIR set for the condition CIR is $0E. Figure 10-20 shows the format of the condition CIR. (UNDEFINED, RESERVED) CONDITION SELECTOR Figure 10-20. Condition CIR Format MOTOROLA MC68030 USER’S MANUAL 10-31...
Page 698 The offset from the base address of the CIR set for the register select CIR is $14. The format of this register depends on the primitive that is currently using it. Refer to 10.4 Coprocessor Response Primitives. 10-32 MC68030 USER’S MANUAL MOTOROLA...
Page 699 Protocol Violations). This processing of undefined primitives supports emulation of extensions to the M68000 coprocessor response primitive set by the protocol violation exception handler. Exception processing related to the coprocessor interface is discussed in 10.5 Exceptions. MOTOROLA MC68030 USER’S MANUAL 10-33...
Page 700 During the execution of conditional category instructions, when the coprocessor terminates the instruction protocol, the MC68030 assumes that the scanPC is pointing to the word following the last of any coprocessor-defined extension words in the instruction format. 10-34 MC68030 USER’S MANUAL MOTOROLA...
Page 701 Exception processing related to concurrent coprocessor instruction execution is discussed in 10.5.1 Coprocessor- Detected Exceptions. MOTOROLA MC68030 USER’S MANUAL 10-35...
Page 702 CIR. When the main processor reads this primitive, it services pending interrupts (using a pre-instruction exception stack frame, refer to Figure 10-41). The processor then restarts the general or conditional coprocessor instruction that it had attempted to initiate earlier. 10-36 MC68030 USER’S MANUAL MOTOROLA...
Page 703 Bit [8], the IA bit, specifies the interrupts allowed optional operation. This bit determines whether the MC68030 services pending interrupts prior to rereading the response CIR after receiving a null primitive. Interrupts are allowed when the IA bit is set. MOTOROLA MC68030 USER’S MANUAL 10-37...
Page 704 CIR (refer to 10.5.2.5 Trace Exceptions). Thus, the main processor continues to read the response CIR until it receives a null, CA=0, PF=1 primitive, and then performs trace exception processing. When IA=1, the main processor services pending interrupts before reading the response CIR again. 10-38 MC68030 USER’S MANUAL MOTOROLA...
Page 705 Else, Execute Next Instruction Coprocessor Instruction Completed; Main Processor Completes Instruction Service Pending Exceptions or Execute Execution Based on TF=c. Next Instruction x = Don't Care c = 1 or 0 Depending on Coprocessor Condition Evaluation MOTOROLA MC68030 USER’S MANUAL 10-39...
Page 706 The transfer operation word primitive requests a copy of the coprocessor instruction operation word for the coprocessor. This primitive applies to general and conditional category instructions. Figure 10-26 shows the format of the transfer operation word primitive. 10-40 MC68030 USER’S MANUAL MOTOROLA...
Page 707 CIR. If the length field is not an even multiple of four bytes, the last two bytes from the instruction stream are transferred using a word write to the operand CIR. MOTOROLA MC68030 USER’S MANUAL 10-41...
Page 708 If the addressing mode in the operation word is not a control alterable mode, the main processor aborts the instruction by writing a $0001 to the control CIR and initiates F-line emulation exception processing (refer to 10.5.2.2 F-Line Emulator Exceptions). 10-42 MC68030 USER’S MANUAL MOTOROLA...
Page 709 Control CIR) to the control CIR and by initiating F-line emulation exception processing. Table 10-4 lists the valid effective address field encodings. Table 10-4. Valid EffectiveAddress Codes Field Category Control Alterable Data Alterable Memory Alterable Alterable Control Data Memory Any Effective Address (No Restriction) MOTOROLA MC68030 USER’S MANUAL 10-43...
Page 710 The DR bit specifies the direction of the operand transfer. DR=0 requests a transfer from the effective address to the operand CIR, and DR=1 specifies a transfer from the operand CIR to the effective address. 10-44 MC68030 USER’S MANUAL MOTOROLA...
Page 711 (A0–A7) using this primitive with the register direct effective addressing mode. A byte or word-sized operand transferred to a data register (D0– D7) only overwrites the lower byte or word of the data register. MOTOROLA MC68030 USER’S MANUAL 10-45...
Page 712 MC68030 is at the user privilege level (S=0 in status register), the MC68030 writes to user data space at the previously calculated program relative address (the 32-bit value in the temporary internal register of the processor). 10-46 MC68030 USER’S MANUAL MOTOROLA...
Page 713 The bus cycles for this operation are normal bus cycles that can be interrupted, and the bus can be arbitrated between the cycles. MOTOROLA MC68030 USER’S MANUAL 10-47...
Page 714 The function code used with the address read from the operand address CIR indicates either supervisor or user data space according to the value of the S bit in the MC68030 status register. 10-48 MC68030 USER’S MANUAL MOTOROLA...
Page 715 The implied effective address mode used for the transfer is the —(A7) addressing mode. A one-byte operand causes the stack pointer to be decremented by two before the transfer to maintain word alignment of the stack. MOTOROLA MC68030 USER’S MANUAL 10-49...
Page 716 This primitive uses the CA, PC, and DR bits as previously described. If the coprocessor issues this primitive with CA=0 during a conditional category instruction, the main processor initiates protocol violation exception processing. 10-50 MC68030 USER’S MANUAL MOTOROLA...
Page 717 After reading a valid code from the register select CIR, if DR=0, the main processor writes the long-word operand from the specified control register to the operand CIR. If DR=1, the main processor reads a long-word operand from the operand CIR and places it in the specified control register. MOTOROLA MC68030 USER’S MANUAL 10-51...
Page 718 If the coprocessor issues this primitive during the execution of a conditional category instruction, the main processor initiates protocol violation exception processing. Figure 10-37 shows the format of the transfer multiple coprocessor registers primitive. 10-52 MC68030 USER’S MANUAL MOTOROLA...
Page 719 The total number of bytes transferred is the product of the number of operands transferred and the length of each operand specified in bits [0-7] of the primitive format. MOTOROLA MC68030 USER’S MANUAL 10-53...
Page 720 OP0, Byte (L-1) is the last byte of the ﬁrst operand written to memory OP1, Byte (0) is the ﬁrst byte of the second operand written to memory OP1, Byte (L-1) is the last byte written to memory Figure 10-38. Operand Format in Memory for Transfer to —(An) 10-54 MC68030 USER’S MANUAL MOTOROLA...
Page 721 By accessing the status register, the coprocessor can determine and manipulate the main processor condition codes, supervisor status, trace modes, selection of the active stack, and interrupt mask level. MOTOROLA MC68030 USER’S MANUAL 10-55...
Page 722 CIR. The MC68030 then proceeds with exception processing as described in 8.1 Exception Processing Sequence. The vector number for the exception is taken from bits [0-7] of the primitive, and the MC68030 uses the four-word stack frame format shown in Figure 10-41. 10-56 MC68030 USER’S MANUAL MOTOROLA...
Page 723 The take mid-instruction exception primitive initiates exception processing using a coprocessor-supplied exception vector number and the mid-instruction exception stack frame format. This primitive applies to general and conditional category instructions. Figure 10-42 shows the format of the take mid-instruction exception primitive. MOTOROLA MC68030 USER’S MANUAL 10-57...
Page 724 CIR. The MC68030 then performs exception processing as described in 8.1 Exception Processing Sequence. The vector number for the exception is taken from bits [0-7] of the primitive and the MC68030 uses the 10-word stack frame format shown in Figure 10-43. 10-58 MC68030 USER’S MANUAL MOTOROLA...
Page 725 MC68030 returns from the exception handler and reads the response CIR. Thus, the main processor attempts to continue executing the suspended instruction by reading the response CIR and processing the primitive it receives. MOTOROLA MC68030 USER’S MANUAL 10-59...
Page 726 Thus, the operation of the MC68030 in response to this primitive is compatible with standard M68000 Family instruction related exception processing (for example, the divide-by-zero exception). 10-60 MC68030 USER’S MANUAL MOTOROLA...
Page 727 The main processor responds to these primitives as previously described. However, not all coprocessor-detected exceptions are signaled by response primitives. Coprocessor- detected format errors during the cpSAVE or cpRESTORE instruction are signaled to the main processor using the invalid format word described in 10.2.3.2.3 Invalid Format Word. MOTOROLA MC68030 USER’S MANUAL 10-61...
Page 728 DSACKx, the main processor waits for the assertion of that signal (or some other bus termination signal) indefinitely. The protocol previously described ensures that the coprocessor cannot halt the main processor. 10-62 MC68030 USER’S MANUAL MOTOROLA...
Page 729 All Motorola M68000 coprocessors signal illegal command and condition words by returning the take pre-instruction exception primitive with the F-line emulator exception vector number 10.5.1.3 COPROCESSOR DATA-PROCESSING EXCEPTIONS.
Page 730 RTE instruction in the handler is executed. If the coprocessor returns the invalid format code when the main processor reads the save CIR to initiate a cpSAVE instruction, the main processor performs format error exception processing as outlined for the cpRESTORE instruction. 10-64 MC68030 USER’S MANUAL MOTOROLA...
Page 731 CIR that is not a valid primitive. The protocol violations that can occur in response to the primitives defined for the M68000 coprocessor interface are summarized in Table 10-6. MOTOROLA MC68030 USER’S MANUAL 10-65...
Page 732 1. If Used with Conditional Instructions 2 .Odd Length Value F-Line: 1. EA Not Control Alterable or (An);pl for CP to Memory Transfer 2. EA Not Control Alterable or —(An) for Memory to CP Transfer 10-66 MC68030 USER’S MANUAL MOTOROLA...
Page 733 Transfer Status and/or ScanPC Protocol: If Used with Conditional Instruction Other: 1. Trace — Trace Made Pending if MC68020 in ``Trace on Change of Flow'' Mode and DR=1 2. Address Error — If Odd value Written to ScanPC Take Pre-Instruction, Mid-Instruction, or Post-Instruction Exception Exception Depends on Vector Supplies in Primitive *Use of this primitive with CA=0 will cause protocol violation on conditional instructions.
Page 734 The exception handler adjusts the program counter field of the saved stack frame to point to the next instruction operation word and executes the RTE instruction. The MC68030 then executes the instruction following the instruction that was emulated. 10-68 MC68030 USER’S MANUAL MOTOROLA...
Page 735 If the exception handler does not modify the stack frame, the main processor executes the instruction following the cpTRAPcc instruction after it executes an RTE instruction to exit from the handler. MOTOROLA MC68030 USER’S MANUAL 10-69...
Page 736 A cpSAVE instruction executed during the trace on change of flow exception handler could thus suspend the execution of a concurrently operating cpGEN instruction. 10-70 MC68030 USER’S MANUAL MOTOROLA...
Page 737 14 when it initiates format error exception processing. Thus, if the exception handler does not modify the stack frame, the main processor attempts to restart the instruction during which the exception occurred after it executes an RTE to return from the handler. MOTOROLA MC68030 USER’S MANUAL 10-71...
Page 738 MC68030. 10.6 COPROCESSOR SUMMARY Coprocessor instruction formats are presented for reference. Refer to the M68000PM/AD, M68000 Programmer's Reference Manual, for detailed information on coprocessor instructions. 10-72 MC68030 USER’S MANUAL MOTOROLA...
Page 739 [13:8]=$00 or $3F causes a protocol violation exception. Response primitives with bits [13:8]=$0B, $18-$1B, $1F, $28-$2B, and $38-3B currently cause protocol violation exceptions; they are undefined and reserved for future use by Motorola. BUSY TRANSFER MULTIPLE COPROCESSOR REGISTERS...
Page 740 TRANSFER SINGLE MAIN PROCESSOR REGISTER REGISTER TRANSFER MAIN PROCESSOR CONTROL REGISTER TRANSFER TO/FROM TOP OF STACK LENGTH TRANSFER FROM INSTRUCTION STREAM LENGTH EVALUATE EFFECTIVE ADDRESS AND TRANSFER DATA VALID EA LENGTH TAKE PRE-INSTRUCTION EXCEPTION VECTOR NUMBER 10-74 MC68030 USER’S MANUAL MOTOROLA...
Page 741 Coprocessor Interface Description TAKE MID-INSTRUCTION EXCEPTION VECTOR NUMBER TAKE POST-INSTRUCTION EXCEPTION VECTOR NUMBER WRITE TO PREVIOUSLY EVALUATED EFFECTIVE ADDRESS LENGTH 10-75 MC68030 USER’S MANUAL MOTOROLA...
Page 742 The execution of an instruction that only accesses on-chip registers can be overlapped entirely with a concurrent data write generated by a previous instruction, if prefetches generated by that instruction are resident in the instruction cache. MOTOROLA MC68030 USER’S MANUAL 11-1...
Page 743 The cache holding register provides instruction words to the pipe, regardless of whether the instruction cache is enabled or disabled. 11-2 MC68030 USER’S MANUAL MOTOROLA...
Page 744 The microsequencer may also request a bus cycle that the bus controller cannot perform immediately. In this case, the bus cycle is queued and the bus controller runs the cycle when the current cycle is complete. MOTOROLA MC68030 USER’S MANUAL 11-3...
Page 745 Instruction Execution Timing Figure 11-1. Block Diagram – Eight Independent Resources 11-4 MC68030 USER’S MANUAL MOTOROLA...
Page 746 From an 8- or 16-bit memory, the processor reads the even word before the odd word. Both the even and odd word are loaded into the cache holding register (and the instruction cache if it is enabled and not frozen). MOTOROLA MC68030 USER’S MANUAL 11-5...
Page 747 (CCea) and the instruction-cache-case time for the remainder of the operation (CCop). The instruction-cache-case times for all instructions and addressing modes are listed in the tables of 11.6 Instruction Timing Tables . 11-6 MC68030 USER’S MANUAL MOTOROLA...
Page 748 Figure 11-12, the best case execution time for instruction B occurs when the instruction- cache-case times for instruction B and instruction A overlap so that the head of instruction B is completely overlapped with the tail of instruction A. MOTOROLA MC68030 USER’S MANUAL 11-7...
Page 749 (rounded up to an integral number of clocks). Similarly, the number of prefetch bus cycles is the average of these two cases rounded up to an integral number of bus cycles. 11-8 MC68030 USER’S MANUAL MOTOROLA...
Page 750 1) MOVE.L (d ,An,Dn),Dn 2) #(data).W,(d ,An) Figure 11-4. Processor Activity – Even Alignment Figure 11-5 shows processor activity for odd alignment. The instruction stream is positioned in 32-bit memory as: Address MOVE EA Ext CMPI #(data.W) n+12 MOTOROLA MC68030 USER’S MANUAL 11-9...
Page 751 11.6 Instruction Timing Tables) , the instruction-cache-case times listed in the tables must be used, and the proper overlap must be subtracted for the entire sequence. The formula for this calculation is: +[CC –min(H )]+[(CC –min(H )]+. . . (11-1) where: 11-10 MC68030 USER’S MANUAL MOTOROLA...
Page 752 MOTOROLA MC68030 USER’S MANUAL 11-11...
Page 753 The underlined numbers show the typical pattern for the com- parison of head and tail in the following equation. The following computations use Equation (11-1): Execution Time = CC1+[CC2-min(H2,T1)] = 2+[4-min(4,0)] = 2+[4-0] = 6 clocks 11-12 MC68030 USER’S MANUAL MOTOROLA...
Page 754 4. TAS (A3)+ Calculate Effective Address (cea) (An)+ TAS Mem 5. NEG D3 The following calculations use Equations (11-1) and (11-2): ExecutionTime = CCea1+[CCop1-min(Hop1,Tea1)]+[CCea2-min(Hea2,Top1)]+ [CCop2-min(Hop2,Tea2)]+[CCea3-min(Hea3,Top2)]+ [CCop3-min(Hop3,Tea3)]+[CCea4-min(Hop4,Top3)]+ [CCop4-min(Hop4,Top3)]+[CCop5-min(Hop5,Top4)] = 4+[2-min(0,2)]+[10-min(4,0)]+[3-min(0,0)]+[3-min(1,1)]+ = [4-min(2,1)]+[2-min(0,0)]+[12-min(3,0)]+[2-min(2,0)] = 4+2+10+3+2+3+2+12+2 = 40 clock periods MOTOROLA MC68030 USER’S MANUAL 11-13...
Page 755 #<data>.L,D1 4+op head ADDI #<data>,Dn 2(op head) The following calculations use the general Equation (11-2): Execution Time: = CCea +[CCop -min(Hop ,Tea ]+[CCea min(Hea ,Top [CCop2-min(Hop2,Tea2)] = 4+[3-min(0,2)]+[4-min(6,1)]+[2-min(2,0)] = 4+3+3+2 = 2 clock periods 11-14 MC68030 USER’S MANUAL MOTOROLA...
Page 756 DIVS.L #$10000,D3:D4 Head Tail 1. MULU.L (D7),D1:D2 fiea #<data>.W,Dn 2+op head MUL.L EA, Dn 2(op head) 2. BFCLR $6000{0:8} fiea #<data>.W,$XXX.W BFCLR Mem(<5 bytes) 3. DIVS.L #$10000,D3:D4 fiea #<data>.W,#<data>.L 6+op head DIVS.L EA,Dn 0(op head) MOTOROLA MC68030 USER’S MANUAL 11-15...
Page 757 –1) where: Tail and CC are the values listed in the tables. 2. If the EA mode is memory indirect (two data reads), the tail and CC time are calculated as for one data read. 11-16 MC68030 USER’S MANUAL MOTOROLA...
Page 758 NOTE It is helpful to include the number of operand reads and writes along with the number of instruction accesses in the CC column for computing the effect of data cache hits on execution time. MOTOROLA MC68030 USER’S MANUAL 11-17...
Page 759 (for the address fetch), add the number of wait states for two reads to the CC time. Add the number of wait states for one data read to the tail. The head is not affected. 11-18 MC68030 USER’S MANUAL MOTOROLA...
Page 760 References are to the preceding rules. Instruction 1. MOVE.L ($800,A2,D3),(A5,D2) 2. ADD.L D1,([$30,A4]) 3. BFCLR ($20,A5){1:5} - (<5 bytes) 4. BFTST ($10,A3,D3){31:31} - (5 bytes) 5. MOVEM ([A1,D1]),A1-A4 - 4 registers MOTOROLA MC68030 USER’S MANUAL 11-19...
Page 761 *Corrected for wait states. NOTE It is helpful to include the number of operand read and writes along with the number of instruction accesses in the CC column for computing the effect of wait states on execution time. 11-20 MC68030 USER’S MANUAL MOTOROLA...
Page 762 , since the read operations hit in the cache and cause no delay. The third line for each timing is used to calculate the instruction cache execution time; it is shown in boldface type. Instruction 1. ADD.L -(A1),D1 2. AND.L D1,([A2]) 3. MOVE.L (A6),(8,A1) 4. TAS (A3)+ MOTOROLA MC68030 USER’S MANUAL 11-21...
Page 763 4. TAS (A3)+ Cea (An) 2(0/0/0) 2(0/0/0) 2(0/0/0) TAS Mem 12(1/0/1) 12(1/0/1) 14(1/0/1) NOTES: *Corrected for data cache hits. **Corrected for wait states also (only on data writes). ***No data cache hit assumed for address fetch. 11-22 MC68030 USER’S MANUAL MOTOROLA...
Page 764 The average no-cache-case timing obtained from this formula is equal to or greater than the actual no-cache-case timing since the number of instruction accesses used is a maximum (the values in the tables are always rounded up) and no overlap is assumed. MOTOROLA MC68030 USER’S MANUAL 11-23...
Page 765 The only instances for which the size of the operand has any effect are the instructions with immediate operands and the ADDA and SUBA instructions. Unless specified otherwise, immediate byte and word operands have identical execution times. 11-24 MC68030 USER’S MANUAL MOTOROLA...
Page 766 The number of read, prefetch, and write cycles is given inside the parentheses as (r/p/w). The read, prefetch, and write cycles are included in the total clock cycle number. MOTOROLA MC68030 USER’S MANUAL 11-25...
Page 767 3(1/0/0) –(An) 4(1/0/0) 4(1/0/0) ,An) or (d ,PC) 4(1/0/0) 4(1/1/0) (xxx).W 4(1/0/0) 4(1/1/0) (xxx).L 4(1/0/0) 5(1/1/0) #〈data〉.B 2(0/0/0) 2(0/1/0) #〈data〉.W 2(0/0/0) 2(0/1/0) #〈data〉.L 4(0/0/0) 4(0/1/0) BRIEF FORMAT EXTENSION WORD 6(1/0/0) 6(1/1/0) ,An,Xn) or ( ,PC,Xn) 11-26 MC68030 USER’S MANUAL MOTOROLA...
Page 768 = Index; 0, Xn % = No clock cycles incurred by effective address fetch. NOTE: Xn cannot be in B and I at the same time. Scaling and size of Xn do not affect timing. MOTOROLA MC68030 USER’S MANUAL 11-27...
Page 769 #〈data〉.L,$XXX.W 8(1/0/0) 8(1/2/0) #〈data〉.W,$XXX.L 6(1/0/0) 7(1/2/0) #〈data〉.L,$XXX.L 8(1/0/0) 9(1/2/0) # 〈data〉.W, #〈data〉. L 6+op head 6(0/0/0) 6(0/2/0) BRIEF FORMAT EXTENSION WORD #〈data〉.W,(d ,An,Xn) or (d ,PC,Xn) 8(1/0/0) 8(1/2/0) #〈data〉.L,(d ,An,Xn) or (d ,PC,Xn) 10(1/0/0) 10(1/2/0) 11-28 MC68030 USER’S MANUAL MOTOROLA...
Page 770 17(2/2/0) #〈data〉.W,([B],I,d 14(2/0/0) 15(2/2/0) #〈data〉.L,([B],I,d 16(2/0/0) 17(2/2/0) #〈data〉.W,([B],d 14(2/0/0) 16(2/2/0) #〈data〉.L,([B],d 16(2/0/0) 18(2/3/0) #〈data〉.W,([B],I,d 14(2/0/0) 16(2/2/0) #〈data〉.L,([B],I,d 16(2/0/0) 18(2/3/0) #〈data〉W,([d ,B]) 14(2/0/0) 15(2/0/0) #〈data〉.L,([d ,B]) 16(2/0/0) 17(2/2/0) #〈data〉.W,([d ,B],I) 14(2/0/0) 15(2/2/0) #〈data〉.L,([d ,B],I) 16(2/0/0) 17(2/2/0) MOTOROLA MC68030 USER’S MANUAL 11-29...
Page 771 The number of read, prefetch, and write cycles is given inside the parentheses as (r/p/w). The read, prefetch, and write cycles are included in the total clock cycle number. All timing data assumes two-clock reads and writes. 11-30 MC68030 USER’S MANUAL MOTOROLA...
Page 772 6(0/1/0) 8(0/0/0) 9(0/1/0) 12(0/0/0) 12(0/2/0) ([B]) 10(1/0/0) 10(1/1/0) ([B],I) 10(1/0/0) 10(1/1/0) ([B],d 12(1/0/0) 13(1/1/0) ([B],I,d 12(1/0/0) 13(1/1/0) ([B],d 12(1/0/0) 13(1/2/0) ([B],I,d 12(2/0/0) 13(1/2/0) ,B]) 12(1/0/0) 13(1/1/0) ,B],I) 12(1/0/0) 13(1/1/0) ,B],d 14(1/0/0) 16(2/2/0) B],I,d 14(1/0/0) 16(2/2/0) MOTOROLA MC68030 USER’S MANUAL 11-31...
Page 773 The number of read, prefetch, and write cycles is given inside the parentheses as (r/p/w). The read, prefetch, and write cycles are included in the total clock cycle number. All timing data assumes two-clock reads and writes. 11-32 MC68030 USER’S MANUAL MOTOROLA...
Page 774 PC],d 16(1/0/0) 17(1/3/0) #〈data〉.W,([d ,An],Xn,d ) or ([d ,PC],Xn,d 14(1/0/0) 15(1/3/0) #〈data〉.L,([d ,An],Xn,d ) or ([d PC],Xn,d 16(1/0/0) 17(1/3/0) % #〈data〉.W,(B) 8 + op head 8(0/0/0) 8(0/1/0) % #〈data〉.L,(B) 10 + op head 10(0/0/0) 10(0/2/0) MOTOROLA MC68030 USER’S MANUAL 11-33...
Page 775 #〈data〉.L,([d ,B],I,d 18(1/0/0) 20(1/3/0) #〈data〉.W,([d ,B]) 18(1/0/0) 19(1/2/0) #〈data〉.L,([d 20(1/0/0) 21(1/3/0) #〈data〉.W,([d ,B],I) 18(1/0/0) 19(1/2/0) #〈data〉.L,([d ,B],I) 20(1/0/0) 21(1/3/0) #〈data〉.W,([d ,B],d 20(1/0/0) 22(1/3/0) #〈data〉.L,([d ,B],d 22(1/0/0) 24(1/3/0) #〈data〉.W,([d ,B],I,d 20(1/0/0) 22(1/3/0) #〈data〉.L,([d ,B],I,d 22(1/0/0) 24(1/3/0) 11-34 MC68030 USER’S MANUAL MOTOROLA...
Page 776 % Dn 2+op head 2(0/0/0) 2(0/0/0) % An 4+op head 4(0/0/0) 4(0/0/0) % (xxx).W 2+op head 2(0/0/0) 2(0/0/0) % (xxx).L 2+op head 2(0/0/0) 2(0/0/0) BRIEF FORMAT EXTENSION WORD ,An,Xn) or (d ,PC,Xn) 6+op head 6(0/0/0) 6(0/0/0) MOTOROLA MC68030 USER’S MANUAL 11-35...
Page 777 % = Total head for effective address timing includes the head time for the operation. NOTE: Xn cannot be in B and I at the same time. Scaling and size of Xn do not affect timing. 11-36 MC68030 USER’S MANUAL MOTOROLA...
Page 778 4(0/0/1) 5(0/1/1) MOVE Rn,–(An) 4(0/0/1) 4(0/1/1) MOVE SOURCE, –(An) 4(0/0/1) 5(0/1/1) MOVE EA, (d ,An) 4(0/0/1) 5(0/1/1) MOVE EA,XXX.W 4(0/0/1) 5(0/1/1) MOVE EA,XXX.L 6(0/0/1) 7(0/2/1) BRIEF FORMAT EXTENSION WORD MOVE EA, (d ,An,Xn) 6(0/0/1) 7(0/1/1) MOTOROLA MC68030 USER’S MANUAL 11-37...
Page 779 21(1/3/1) MOVE EA,([d ,B],d 20(1/0/1) 23(1/3/1) MOVE EA,([d ,B],I,d 20(1/0/1) 23(1/3/1) Add Fetch Effective Address Time SOURCE Is Memory or Immediate Data Address Mode Rn Is a Data or Address Register Is any Effective Address 11-38 MC68030 USER’S MANUAL MOTOROLA...
Page 780 MOVEM EA,RL – For n Registers (n > 0) and w Wait States w ≤ 2: (4+2n)+(n–1)w Add Fetch Effective Address Time I-Cache Case Timing = Add Calculate Immediate Address Time w > 2: (4+2n)+(n–1)w+(w–2) w ≤ 2: (n–1)w Tail = w > 2: (n)w+(n)(w–2) MOTOROLA MC68030 USER’S MANUAL 11-39...
Page 781 2(0/0/0) 2(0/1/0) Dn,EA 3(0/0/1) 4(0/1/1) Dn,Dn 2(0/0/0) 2(0/1/0) EA,Dn 2(0/0/0) 2(0/1/0) Dn,EA 3(0/0/1) 4(0/1/1) Dn,Dn 2(0/0/0) 2(0/1/0) Dn,EA 3(0/0/1) 4(0/1/1) Dn,Dn 2(0/0/0) 2(0/1/0) EA,Dn 2(0/0/0) 2(0/1/0) Dn,EA 3(0/0/1) 4(0/1/1) Rn,Dn 2(0/0/0) 2(0/1/0) EA,Dn 2(0/0/0) 2(0/1/0) 11-40 MC68030 USER’S MANUAL MOTOROLA...
Page 782 44(0/0/0) 44(0/1/0) ** + DIVU.L Dn,Dn 78(0/0/0) 78(0/1/0) ** + DIVU.L EA,Dn 78(0/0/0) 78(0/1/0) * Add Fetch Effective Address Time **Add Fetch Immediate Effective Address Time + Indicates Maximum Time (Acutal time is data dependent) MOTOROLA MC68030 USER’S MANUAL 11-41...
Page 783 4(0/1/1) #〈data〉,Dn 2(0/0/0) 2(0/1/0) #〈data〉,Mem 3(0/0/1) 4(0/1/1) SUBI #〈data〉,Dn 2(0/0/0) 2(0/1/0) SUBI #〈data〉,Mem 3(0/0/1) 4(0/1/1) CMPI #〈data〉,Dn 2(0/0/0) 2(0/1/0) CMPI #〈data〉,Mem 2(0/0/0) 2(0/1/0) * Add Fetch Effective Address Time **Add Fetch Immediate Effective Address Time 11-42 MC68030 USER’S MANUAL MOTOROLA...
Page 784 Dn,Dn 2(0/0/0) 2(0/1/0) ADDX –(An),–(An) 9(2/0/1) 10(2/1/1) SUBX Dn,Dn 2(0/0/0) 2(0/1/0) SUBX –(An) 9(2/0/1) 10(2/1/1) CMPM (An)+,(An)+ 8(2/0/0) 8(2/1/0) PACK Dn,Dn,#〈data〉 6(0/0/0) 6(0/1/0) PACK –(An),–(An),#〈data〉 11(1/0/1) 11(1/1/1) UNPK Dn,Dn,#〈data〉 8(0/0/0) 8(0/1/0) UNPK –(An),–(An),#〈data〉 11(1/0/1) 11(1/1/1) MOTOROLA MC68030 USER’S MANUAL 11-43...
Page 785 NEGX 3(0/0/1) 4(0/1/1) 2(0/0/0) 2(0/1/0) 3(0/0/1) 4(0/1/1) 4(0/0/0) 4(0/1/0) NBCD 6(0/0/0) 6(0/1/0) 4(0/0/0) 4(0/1/0) 5(0/0/1) 5(0/1/1) 4(0/0/0) 4(0/1/0) 12(1/0/1) 12(1/1/1) 2(0/0/0) 2(0/1/0) 2(0/0/0) 2(0/1/0) * Add Fetch Effective Address Time **Add Calculate Effective Address Time 11-44 MC68030 USER’S MANUAL MOTOROLA...
Page 786 4(0/1/0) Direction of shift/rotate: L or R Add Fetch Effective Address Time % Indicates shift count is less than or equal to the size of data Indicates shift count is greater than size of data MOTOROLA MC68030 USER’S MANUAL 11-45...
Page 787 6(0/0/1) 6(0/1/1) BCLR Dn,Mem 6(0/0/1) 6(0/1/1) BSET #〈data〉,Dn 6(0/0/0) 6(0/1/0) BSET Dn,Dn 6(0/0/0) 6(0/1/0) BSET #〈data〉,Mem 6(0/0/1) 6(0/1/1) BSET Dn,Mem 6(0/0/1) 6(0/1/1) * Add Fetch Effective Address Time # Add Fetch Immediate Effective Address Time 11-46 MC68030 USER’S MANUAL MOTOROLA...
Page 788 *Add Calculate Immediate Effective Address Time NOTE: A bit ﬁeld of 32 bits may span 5 bytes that require two operand cycles to access or may span 4 bytes that require only one operand cycle to access. MOTOROLA MC68030 USER’S MANUAL 11-47...
Page 789 4(0/0/0) 4(0/1/0) Bcc.W (Not Taken) 6(0/0/0) 6(0/1/0) Bcc.L (Not Taken) 6(0/0/0) 8(0/2/0) DBcc (cc = False, Count Not Expired) 6(0/0/0) 8(0/2/0) DBcc (cc = False, Count Expired) 10(0/0/0) 13(0/3/0) DBcc (cc = True) 6(0/0/0) 8(0/1/0) 11-48 MC68030 USER’S MANUAL MOTOROLA...
Page 790 12(2/0/0) 14(2/2/0) 9(1/0/0) 11(1/2/0) UNLK 5(1/0/0) 5(1/1/0) Indicates Maximum Time Add Fetch Immediate Address Time Add Fetch Effective Address Time Add Calculate Immediate Address Time Add Calculate Effective Address Time Add Jump Effective Address Time MOTOROLA MC68030 USER’S MANUAL 11-49...
Page 791 TRAPcc (Trap) 22(1/0/5) 24(1/2/5) TRAPcc (No Trap) 4(0/0/0) 4(0/1/0) TRAPcc.W (Trap) 24(1/0/5) 26(1/3/5) TRAPcc.W (No Trap) 6(0/0/0) 6(0/1/0) TRAPcc.L (Trap) 26(1/0/5) 28(1/3/5) TRAPcc.L (No Trap) 8(0/0/0) 8(0/2/0) TRAPV (Trap) 22(1/0/5) 24(1/2/5) TRAPV (No Trap) 4(0/0/0) 4(0/1/0) 11-50 MC68030 USER’S MANUAL MOTOROLA...
Page 792 Use the time required for two bus cycles in the case of a 16-bit data bus. Use the time required for four bus cycles in the case of an 8-bit data bus. UNIX is a registered trademark of AT&T Bell Laboratories. MOTOROLA MC68030 USER’S MANUAL 11-51...
Page 793 The times provided by this program include all phases of the translation tree search. With various mask versions of the MC68030, times may differ slightly from those calculated by the program. (UNABLE TO LOCATE ART) 11-52 MC68030 USER’S MANUAL MOTOROLA...
Page 794 Instruction Execution Timing (UNABLE TO LOCATE ART) MOTOROLA MC68030 USER’S MANUAL 11-53...
Page 795 Instruction Execution Timing (UNABLE TO LOCATE ART) 11-54 MC68030 USER’S MANUAL MOTOROLA...
Page 796 Instruction Execution Timing (UNABLE TO LOCATE ART) MOTOROLA MC68030 USER’S MANUAL 11-55...
Page 797 41/4/2 37/4/1 35/4/0 LLLxx 53/6/3 45/6/1 43/6/0 LLLLx 65/8/4 53/8/1 51/8/0 LLLLL 77/10/5 61/10/1 59/10/0 SSxxx 37/2/2 33/2/1 31/2/0 SSSxx 46/3/3 38/3/1 36/3/0 SSSSx 55/4/4 43/4/1 41/4/0 SSSSS 64/5/5 48/5/1 46/5/0 xSSxx 39/2/2 35/2/1 33/2/0 11-56 MC68030 USER’S MANUAL MOTOROLA...
Page 798 ,An],Xn,d 14(1/0/0) 14(1/3/0) 8+op head 8(0/0/0) 8(0/1/0) 10(0/0/0) 10(0/2/0) 16(0/0/0) 16(0/2/0) ([B]) 12(1/0/0) 12(1/1/0) ([B],I) 12(1/0/0) 12(1/1/0) ([B],d 12(1/0/0) 12(1/2/0) ([B],I,d 12(1/0/0) 12(1/2/0) ([B],d 14(1/0/0) 14(1/2/0) ([B],I,d 14(1/0/0) 14(1/2/0) ,B]) 14(1/0/0) 14(1/2/0) ,B],I) 14(1/0/0) 14(1/2/0) MOTOROLA MC68030 USER’S MANUAL 11-57...
Page 799 Instruction Execution Timing FULL FORMAT EXTENSION WORD(S) ,B],d 14(1/0/0) 14(1/2/0) ,B],I,d 14(1/0/0) 14(1/2/0) ,B],I,d 16(1/0/0) 16(1/3/0) 11-58 MC68030 USER’S MANUAL MOTOROLA...
Page 800 *No separation on effective address and operation in timing. Head and tail are the operation's. NOTE: Xn cannot be in B and I at the same time. Scaling and size of Xn do not affect timing. MOTOROLA MC68030 USER’S MANUAL...
Page 801 ** Add the appropriate effective address calculation time and the table search time. *** Number given is the maximum for a six-level table (FC lookup, a, b, c, and d levels with indirect level, all long descriptors). 11-60 MC68030 USER’S MANUAL MOTOROLA...
Page 802 For example, if the language translators in the system only generate long words aligned on long-word boundaries, the indirect address and operands can cause only one translation search each. This reduces the number of searches for the instruction to a maximum of six. MOTOROLA MC68030 USER’S MANUAL 11-61...
Page 803 Another bus arbitration delay occurs when a coprocessor or other device delays or fails to assert DSACKx or STERM signals to terminate a bus cycle. The maximum delay in this case is undefined; it depends on the length of the delay in asserting the signals. 11-62 MC68030 USER’S MANUAL MOTOROLA...
Page 804 This section provides guidelines for using the MC68030. First, it discusses the requirements for adapting the MC68030 to MC68020 designs. Then, it describes the use of the MC68881 and MC68882 coprocessors with the MC68030. The byte select logic is described next, followed by memory interface information.
Page 805 (e.g., lighting an LED) that the processor has halted due to a double bus fault. When used in a system originally designed for both an MC68020 and an MC68851, the MC68851 may be left in the system or removed (and replaced with a jumpered header).
Page 806 DSACK1 DSACK0 DSACK0 RESET SIZ0 SIZ0 RESET SIZ1 SIZ1 DBEN DBEN CDIS CDIS CIOUT CBREQ D31–D0 D31–D0 CBACK CIIN FC2–FC0 FC2–FC0 STERM A31–A0 A31–A0 Figure 12-1. Signal Routing for Adapting the MC68030 to MC68020 Designs MOTOROLA MC68030 USER’S MANUAL 12-3...
Page 807 MC68030 does not support the CALLM and RTM instructions of the MC68020. If code is executed on the MC68030 using either the CALLM or RTM instructions, an unimplemented instruction exception is taken. If no MMU software development capability is desired and the cache behavior described under hardware differences is understood, the user may ignore the MC68030 MMU.
Page 808 MC68881/MC68882 for smaller data bus widths. Note that the MC68030 cache inhibit input (CIIN) signal is not used for the coprocessor interface because the MC68030 does not cache data obtained during CPU space accesses. MOTOROLA MC68030 USER’S MANUAL 12-5...
Page 809 Coprocessor Interface Description for more information concerning the encoding of these signals. All or just a subset of these lines may be decoded depending on the number of coprocessors in the system and the degree of redundant mapping allowed in the system. 12-6 MC68030 USER’S MANUAL MOTOROLA...
Page 810 CPU space type as coprocessor space ($2). A13–A15 can be ignored in this case because they encode the coprocessor identification code (CpID) used to differentiate between multiple coprocessors in a system. Motorola assemblers always default to a CpID of $1 for floating-point instructions; this can be controlled with assembler directives if a different CpID is desired or if multiple coprocessors exist in the system.
Page 811 • R/W = Read/Write. Output of the MC68030. For byte select generation in MC68030 systems, R/W must be included in the logic if the data from the device is cach- able. 12-8 MC68030 USER’S MANUAL MOTOROLA...
Page 812 Figure 12-6 shows a block diagram of an MC68030 system with two memory banks. The PAL provides memory-mapped byte select signals for an asynchronous 32-bit port and unmapped byte select signals for other memory banks or ports. Figure 12-7 provides sample equations for the PAL. MOTOROLA MC68030 USER’S MANUAL 12-9...
Page 813 3. Burst operation cycles, terminated by the STERM and CBACK signals, have a dura- tion of as little as five processor clock periods in which up to four long words (16 bytes) are transferred. 12-10 MC68030 USER’S MANUAL MOTOROLA...
Page 814 Applications Information Figure 12-6. Example MC68030 Byte Select PAL System Configuration 12-12 MC68030 USER’S MANUAL MOTOROLA...
Page 815 “no wait states” regardless of the external memory configuration. This feature makes the MC68030 (and MC68020) unique among other general-purpose microprocessors. 12.4.1 Access Time Calculations The timing paths that are typically critical in any memory interface are illustrated and defined in Figure 12-8.
Page 816 #31. With a 16.67-MHz processor, this time is 50 ns after DSACKx asserts; with a 20.0-MHz processor, this time is 43 ns after DSACK asserts (both numbers vary with the actual clock frequency). 12-14 MC68030 USER’S MANUAL MOTOROLA...
Page 817 Note that other devices in the system may require qualification of the access with AS since the MC68030 has the capability to initiate bus cycles and then abort them before the assertion of AS. MOTOROLA MC68030 USER’S MANUAL 12-15...
Page 818 Thus, the access time for the first cycle determines the critical timing paths. 12-16 MC68030 USER’S MANUAL MOTOROLA...
Page 819 AND gate. The memory bank can be divided into three sections: 1. The byte select and address decode section (provided by the PAL), 2. The actual memory section (SRAMs), and 3. The buffer section. MOTOROLA MC68030 USER’S MANUAL 12-17...
Page 820 SRAMs before the negation of the write strobes (W). TERM is then connected to the system's STERM consolidation circuity. The consolidation circuitry should have no more than 15 ns of propagation delay. If the system has no other synchronous memory or ports, TERM may be connected directly to STERM. 12-18 MC68030 USER’S MANUAL MOTOROLA...
Page 821 BERR, HALT D31-D0 NOTE: This diagram illustrates access time calculations only. DSACK1/DSACK0 and STERM should never be asserted together during the same bus cycle. FIG 12-10 Figure 12-10. Example PAL Equations for Two-Clock Memory Bank MOTOROLA MC68030 USER’S MANUAL 12-19...
Page 822 (8) 16K*4 SRAMs, 25-ns access time with separate I/O pins (4) 74F244 buffers (2) 74F32 OR gates (1) PAL16L8D (or equivalent) (1) 74F74 D-type flip-flop (2) 74F373 transparent latches (1) 74AS21 AND gate (1) 74F04 inverter 12-20 MC68030 USER’S MANUAL MOTOROLA...
Page 823 (W) negate. During read operations, the transparent latches on the address lines remain in the transparent mode, allowing the SRAMs to provide data through the 74F244 buffers in time to meet the specified data setup time to the MC68030. MOTOROLA MC68030 USER’S MANUAL 12-21...
Page 824 This can be accomplished with the addition of a flip-flop to delay the TERM signal by one clock. The resulting memory access time is over 85 ns with a 20-MHz processor running with three-clock bus cycles. 12-22 MC68030 USER’S MANUAL MOTOROLA...
Page 825 Nonburst reads and all write cycles execute in two clocks. Figure 12-14 shows the complete memory bank and its connection to the MC68030. The required parts include: (32) 64K x 1 SRAMs 25 ns access time (Motorola's MCM6287-25 or equivalent) (2) 74ALS244 buffers (4) 74AS373 latches...
Page 826 CBREQ signal and the CLK signal. During writes, CBREQ is always negated, and the counters serve only as address buffers. During reads, if CBREQ asserts, the current value of counter bits Q1:Q0 are incremented on every falling 12-24 MC68030 USER’S MANUAL MOTOROLA...
Page 827 If the designer wishes to include some type of enable circuitry to take advantage of low bus utilization, the timing in this design will be preserved if the memory's E signal is asserted within 13 ns after the falling edge of state S0. MOTOROLA MC68030 USER’S MANUAL 12-25...
Page 828 Figure 12-15 shows the complete 3-1-1-1 memory bank with 256K bytes that can operate with a 20-MHz MC68030. The required parts include: (32) 64K x 1 SRAMs 35-ns access time (Motorola's MCM6287-35 or equivalent) (4) 74ALS244 buffers (4) 74F374 latches...
Page 829 E signal is asserted within 10 ns after the rising edge of state S2. Figure 12-16 shows four possible enable circuits. (UNABLE TO LOCATE ART) Figure 12-16. Additional Memory Enable Circuits MOTOROLA MC68030 USER’S MANUAL 12-27...
Page 830 (BERR and HALT) are negated soon enough after the completion of the aborted cycle that the next cycle can begin immediately. In evaluating this overhead, the projected cache miss rate 12-28 MC68030 USER’S MANUAL MOTOROLA...
Page 831 (although the control circuitry required may be more complex). MOTOROLA MC68030 USER’S MANUAL 12-29...
Page 832 Conversely, if the cache size is relatively large and the period between context switches is relatively small, the cache may provide an efficient sharing of entries. 12-30 MC68030 USER’S MANUAL MOTOROLA...
Page 833 Equation 12-5 of Table 12-2). The only required changes to the cache structure shown in Figure 12-17 is the generation of STERM. Figure 12-18 shows an example circuit that could be positioned between the MC68030 and the external cache to provide the early termination or late retry function. MOTOROLA MC68030 USER’S MANUAL 12-31...
Page 834 Other conditions to suppress early termination may be included as required by a particular system, but propagation delays must be carefully considered in order that the output of (C) be valid before the rising edge of state S1 (see Equation 12-3 of Table 12-2). 12-32 MC68030 USER’S MANUAL MOTOROLA...
Page 835 A provision for generating wait states may be included by placing additional timing stages between (C) and the MC68030 to delay propagation of this output by the required number of clock periods. MOTOROLA MC68030 USER’S MANUAL 12-33...
Page 836 The MC68030 supports the monitoring of internal microsequencer activity with the STATUS and REFILL signals. The use of these signals is described in the following paragraph. A useful device to aid programming debugging is described in 12.7.2 Real-Time Instruction Trace. 12-34 MC68030 USER’S MANUAL MOTOROLA...
Page 837 Similarly, operations which affect the address translation mechanism of the memory management unit (MMU) cause a refill request. An instruction like the PMOVE <ea>,TC, which changes the translation control register, requires the processor to fetch data MOTOROLA MC68030 USER’S MANUAL 12-35...
Page 838 Instruction boundary information is still present since both trace and interrupt exceptions are processed only at instruction boundaries. Before the exception handler instructions are prefetched, the REFILL signal asserts (not shown) to identify a change in program flow. 12-36 MC68030 USER’S MANUAL MOTOROLA...
Page 839 The processor also halts if it receives a bus error or address error during the vector table read operations or the prefetch for the first instruction after an external reset. STATUS remains asserted until the processor is reset. MOTOROLA MC68030 USER’S MANUAL 12-37...
Page 840 Both modes of bus operation need to generate a sampling signal when valid data is present on the bus. This allows for tracing data flow in and out of the processor, which is the basis for tracking program execution. 12-38 MC68030 USER’S MANUAL MOTOROLA...
Page 841 CLK signal for synchronization. Setting up the logic analyzer for data capture requires that samples be taken on the falling edge of the CLK signal when the SAMPLE signal is high. Table 12-5 lists the parts required to implement this circuit. 12-39 MC68030 USER’S MANUAL MOTOROLA...
Page 842 F-line instruction, MMU address translation cache miss, trace exception, or interrupt exception. The EP signal asserts after STATUS negates from a two- or three-clock cycle assertion. The assertion of EP does generate a SAMPLE signal. 12-40 MC68030 USER’S MANUAL MOTOROLA...
Page 843 These definitions are used by the PAL equations listed in Figure 12-25. 12.8 POWER AND GROUND CONSIDERATIONS The MC68030 is fabricated in Motorola's advanced HCMOS process, contains approximately 275,000 total transistor sites, and is capable of operating at clock frequencies of up to 33.33 MHz.
Page 844 10 µF, 0.1 µF, and 330 pF capacitors in parallel provides filtering for most frequencies prevalent in a digital system). Similar decoupling techniques should also be observed for other VLSI devices in the system. 12-42 MC68030 USER’S MANUAL MOTOROLA...
Page 845 Failure to provide connections of sufficient quality between the MC68030 power supply pins and the system supplies will result in increased assertion delays for external signals, decreased voltage noise margins, and potential errors in internal logic. 12-43 MC68030 USER’S MANUAL MOTOROLA...
Page 846 *A continuous clock must be supplied to the MC68030 when it is powered up. 13.2 THERMAL CHARACTERISTICS — PGA PACKAGE Characteristic Symbol Value Rating ° C/W Thermal Resistance - Plastic θ Junction to Ambient Junction to case θ *Estimated MOTOROLA MC68030 USER’S MANUAL 13-1...
Page 847 0 ° C to 70 ° C 33.33 MC68030RC33 0 ° C to 70 ° C Ceramic Surface Mount 20.0 MC68030FE20 0 ° C to 70 ° C FE Suffix 25.0 MC68030FE25 0 ° C to 70 ° C 33.33 MC68030FE33 MOTOROLA MC68030 USER’S MANUAL 14-1...
Page 848 FC0-FC2, RMC, OCS, CIOUT, BG Internal Logic, RESET, STATUS, REFILL, Misc. H3, F2, F11, H11 L8, G3, F3, G11 (UNABLE TO LOCATE ART) 14.3 PIN ASSIGNMENTS — CERAMIC SURFACE MOUNT (FE SUFFIX) (UNABLE TO LOCATE ART) 14-2 MC68030 USER’S MANUAL MOTOROLA...
Page 849 Ordering Information and Mechanical Data 14.4 PACKAGE DIMENSIONS MC68030 RC Suffix Package Case 789C-01 (UNABLE TO LOCATE ART) MOTOROLA MC68030 USER’S MANUAL 14-3...
Page 850 Ordering Information and Mechanical Data MC68030 FE Suffix Package Case 831-01 (UNABLE TO LOCATE ART) 14-4 MC68030 USER’S MANUAL MOTOROLA...
Page 851 Data Cache (in words) — — — — Note 1. The MC68010 supports a three-word cache for the loop mode. Virtual Memory/Machine MC68010, MC68020, and Provide Bus Error Detection, Fault Recovery MC68030 MC68030 On-Chip MMU Coprocessor Interface MC68000, MC68008, and...
Page 852 M68000 Family Summary Word/Long-Word Data Alignment MC68000, MC68008, and Word/Long Data, Instructions, and Stack Must be MC68010 Word Aligned MC68020 and Only Instructions Must be Word Aligned MC68030 (Data Alignment Improves Performance) Control Registers MC68000 and MC68008 None MC68010 SFC, DFC, VBR...
Page 853 M68000 Family Summary Function Code/Address Space MC68000 and MC68008 FC0–FC2=7 is Interrupt Acknowledge Only MC68010, MC68020, and FC0–FC2=7 is CPU Space MC68030 Indivisible Bus Cycles MC68000, MC68008, and Use AS Signal MC68010 MC68020 and MC68030 Use RMC Signal Stack Frames...
Page 854 M68000 Family Summary MC68020 and MC68030 Instruction Set Extensions Supports 32-Bit Displacements BFxxxx Bit Field Instructions (BFCHG, BFCLR, BFEXTS, BFEXTU, BFFFO, BFINS, BFSET, BFTST) BKPT New Instruction Functionality Supports 32-Bit Displacements Supports 32-Bit Displacements CALLM New Instruction (MC68020 only) CAS, CAS2...
Page 855 Bus Operation 7-27 Odd Alignment 11-10 Byte Actual Instruction Cache Case 11-11 Read Cycle Flowchart 7-31 Adapter Board Read Cycle, 32-Bit Port, Timing 7-31 MC68020 12-1 Read-Modify-Write Cycle, 32-Bit Signal Routing 12-2 Port, Timing 7-43 Address Bus 5-4, 7-4, 7-30, 12-4...
Page 856 Fault Recovery 8-27 Instructions 3-8 Operation BKPT Instruction 7-74, 8-12, 8-22 Asynchronous 7-27 Block Diagram 1-2, 9-2 Synchronous 7-28–7-29 MMU 9-2 Synchronization 7-95 Processor Resource 11-3 Timing 7-96 BR Signal 5-8, 7-43, 7-60, 7-96 Transfer Signals 7-1 Index MOTOROLA MC68030 USER’S MANUAL...
Page 857 Command Words, Illegal, Coprocessor CACR 1-5, 2-5, 6-3–6-4, 6-20 Detected 10-63 Calculate Effective Address Timing Table Compare and Swap Instruction 7-43 11-30 Compatibility, M68000 Addressing 2-36 Calculate Immediate Effective Address Computation, Condition Code 3-15 Timing Concurrent Operation 10-3 Index-3 MOTOROLA MC68030 USER’S MANUAL...
Page 858 System Related Exceptions 10-64 Data Burst Enable Bit 6-21 Coprocessor Detected Data Strobe Signal 5-6, 7-5, 7-27 Exceptions 10-61 Data Transfer and Size Acknowledge Signals Format Errors 10-64 5-6, 6-11, 6-14, 7-5–7-6, 7-26 Illegal Command Words 10-63 Index MOTOROLA MC68030 USER’S MANUAL...
Page 859 Linked List Descriptors, Translation Table 9-10, 9-20 Deletion 3-27 DFC 1-8, 2-2, 2-5 Insertion 3-26 Differences Protection, Translation Tree 9-50 MC68020 Hardware 12-3 System Paging Implementation 9-72 MC68020 Software 12-4 Table Paging 9-37 MMU 9-51 Table Sharing 9-34 DMA Coprocessor 10-5...
Page 860 Function Code Signals 5-4, 6-6, 7-4, 7-31 Emulator Exceptions 8-10, 10-68 Floating Point Units 12-5 Flowchart Address Translation, General 9-13 General Description 1-1 Asynchronous Byte Read Cycle 7-31 GetFrame Routine 9-74 Asynchronous Long Word Read Cycle GND Pin Assignments 12-46 Index MOTOROLA MC68030 USER’S MANUAL...
Page 861 Move Address Space 7-74 Memory 12-11 MOVES 7-74 Internal Microsequencer Status Signal 5-10, No Operation 7-95 7-94 NOP 7-95 Internal Operand Representation 7-7 Set on Coprocessor Condition 10-15 Internal to External Data Bus Multiplexer 7-10 STOP 8-14 Interrupt Index-7 MOTOROLA MC68030 USER’S MANUAL...
Page 862 With DSACKx, Timing 7-83 Main Processor Detected Late Retry Operation, Burst, Timing 7-89 Format Errors 10-71 Latency Protocol Violations 10-67 Bus Arbitration 11-62 MC68020 Interrupt 11-61 Adapter Board 12-1 Levels, Interrupt 8-16 Hardware Differences 12-3 Limit Check Procedure Flowchart 9-43 Software Differences 12-4...
Page 863 Operation Word CIR 10-31 Preindexed 2-15 Operations, Bit Field 3-31 Program Counter Ordering Information 14-1 Indirect Displacement 2-16 Organization Indirect Index (Base Displacement) Cache 6-3 2-17 Data Port 7-8 Indirect Index (8-Bit Displacement) Memory Data 2-5 2-16 Index-9 MOTOROLA MC68030 USER’S MANUAL...
Page 864 Register 10-50, 10-52 Transfer Multiple Coprocessor Registers 10-52 Queue 2-39 Transfer Multiple Main Processor Registers 10-52 Transfer Operation Word 10-40 RAM, Static 12-18 Transfer Single Main Processor Register Ratings, Maximum 13-1 10-50, 10-52 Read Cycle Index MOTOROLA MC68030 USER’S MANUAL...
Page 865 Address Map 9-49 Request, Bus 7-98 Sharing, Table 9-37 Requirements, Data Bus, Read Cycle 7-9 Shift Instructions 3-7 Reset Shift/Rotate Instruction Timing Table 11-45 Cache 6-20 Short Format Coprocessor 10-72 Early Termination Page Descriptor 9-25 Exception 8-5 Index-11 MOTOROLA MC68030 USER’S MANUAL...
Page 866 Transfer Size 5-4, 7-4, 7-8–7-9, 7-22 HALT 5-9, 7-6, 7-27 Single Entry Cache Filling 6-10 Halt 5-9, 7-6, 7-27 Single Operand Instruction Timing Table Internal Microsequencer Status 5-10, 11-44 7-94, 8-4, 8-18, 8-25 Size Restrictions, Table Index 9-10 Index MOTOROLA MC68030 USER’S MANUAL...
Page 867 Timing 11-52 Root Pointer 1-9, 2-5, 9-23, 9-52, 9-54, Script 11-52 9-65 Table 11-57 Translation Tree 9-48 Tables, Instruction Timing 11-24 Supervisor Check Primitive 10-40 Take Address and Transfer Data Primitive Supervisor Only Protection 9-48 Index-13 MOTOROLA MC68030 USER’S MANUAL...
Page 868 Jump Effective Address 11-35 CBACK Negated 7-61 Operand Request, Burst Request, Effective Address 11-58 Wait States 7-61 Instruction 11-60 Operand Request, Burst, CBACK MOVE Instruction 11-37 and CIIN Assert 7-61 Special Purpose 11-39 Read Cycle, 16-Bit Port 7-31 Index MOTOROLA MC68030 USER’S MANUAL...
Page 869 Tree, Translation Table 9-5–9-6, 9-11, 9-28, Word, Special Status 8-28 9-47–9-48, 9-65 Write Allocate Bit 6-21 TT0 1-9, 2-5, 9-16, 9-57 Write Cycle TT1 1-9, 2-5, 9-16, 9-57 Asynchronous 7-37 Two Clock Synchronous Static RAM 12-18 Index-15 MOTOROLA MC68030 USER’S MANUAL...
Page 870 32-Bit Port, Timing 7-37 Synchronous 7-51 Flowchart 7-52 Wait States, CIOUT Asserted, Timing 7-52 Write Pending Buffer 11-5 Write Protection 9-48 Write Timing Long Word 7-10 Word 7-13 Write to Previously Evaluated Effective Address Primitive 10-46 Index MOTOROLA MC68030 USER’S MANUAL...
Page 871 µ MOTOROLA M68040 User’s Manual Including the MC68040, MC68040V, MC68LC040, MC68EC040, MC68EC040V ©MOTOROLA INC., 1990 Revised 1992, 1993...
Page 872 Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur.
Page 873 Section 11 MC68040 Electrical and Thermal Characteristics Section 12 Ordering Information and Mechanical Data Appendix A MC68LC040 Appendix B MC68EC040 Appendix C MC68040V and MC68EC040V Appendix D M68000 Family Summary Appendix E Floating-Point Emulation (M68040FPSP) Index M68040 USER’S MANUAL MOTOROLA...
Page 874 Integer Unit Supervisor Programming Model ........2-5 2.2.2.1 Interrupt and Master Stack Pointers ..........2-6 2.2.2.2 Status Register ................2-7 2.2.2.3 Vector Base Register ..............2-7 2.2.2.4 Alternate Function Code Registers ..........2-7 2.2.2.5 Cache Control Register ..............2-8 M68040 USER’S MANUAL MOTOROLA...
Page 875 Effect of RSTI on the MMUs .............. 3-31 3.6.2 Effect of MDIS on Address Translation ..........3-31 MMU Instructions .................. 3-33 3.7.1 MOVEC ..................... 3-33 3.7.2 PFLUSH..................... 3-33 3.7.3 PTEST ....................3-33 3.7.4 Register Programming Considerations..........3-34 MOTOROLA M68040 USER’S MANUAL...
Page 876 Transfer Size (SIZ1, SIZ0) ..............5-7 5.3.7 Lock (LOCK) ..................5-7 5.3.8 Lock End (LOCKE) ................5-7 5.3.9 Cache Inhibit Out (CIOUT) ..............5-8 Bus Transfer Control Signals ..............5-8 5.4.1 Transfer Start (TS) ................5-8 viii M68040 USER’S MANUAL MOTOROLA...
Page 877 Test Reset (TRST)—Not on MC68040V and MC68EC040V..... 5-15 5.13 Power Supply Connections ..............5-15 5.14 Signal Summary ..................5-16 Section 6 IEEE 1149.1 Test Access Port (JTAG) Overview ....................6-2 Instruction Shift Register ............... 6-3 6.2.1 EXTEST ..................... 6-3 MOTOROLA M68040 USER’S MANUAL...
Page 878 6.2.8 BYPASS .................... 6-6 Boundary Scan Register ............... 6-6 Restrictions ................... 6-12 Disabling The IEEE Standard 1149.1A Operation ........ 6-13 Motorola M68040 BSDL Description (Version 2.2) ....... 6-15 MC68040, MC68LC040, MC68EC040 JTAG Electrical Characteristics ............6-21 Section 7 Bus Operation Bus Characteristics ................
Page 879 Eight-Word Stack Frame (Format $4)..........8-23 8.4.6 Access Error Stack Frame (Format $7) ..........8-24 8.4.6.1 Effective Address ................8-24 8.4.6.2 Special Status Word (SSW) ............8-24 8.4.6.3 Write-Back Status ................8-26 8.4.6.4 Fault Address ................. 8-26 MOTOROLA M68040 USER’S MANUAL...
Page 880 Nonmaskable Exception Conditions ..........9-27 9.7.3 Operand Error ................... 9-28 9.7.3.1 Maskable Exception Conditions............. 9-29 9.7.3.2 Nonmaskable Exception Conditions ..........9-30 9.7.4 Overflow .................... 9-31 9.7.4.1 Maskable Exception Conditions............. 9-31 9.7.4.2 Nonmaskable Exception Conditions ..........9-31 M68040 USER’S MANUAL MOTOROLA...
Page 881 MC68040 Power Considerations ............11-12 11.9 MC68040 Thermal Management Techniques ........11-14 11.9.1 Still Air....................11-17 11.9.2 Forced Air ..................11-18 11.9.3 With Heat Sink ................... 11-19 11.9.4 With Heat Sink and Forced Air ............11-22 MOTOROLA M68040 USER’S MANUAL xiii...
Page 882 Input AC Timing Specifications............A-12 Appendix B MC68EC040 MC68EC040 Differences ..............B-4 JTAG Scan (JS1–JS0) ................B-5 Access Control Units................B-5 B.3.1 Access Control Registers ..............B-5 B.3.2 Address Comparison ................. B-7 B.3.3 Effect of RSTI on the ACU..............B-8 M68040 USER’S MANUAL MOTOROLA...
Page 883 C.6.1.3 SAMPLE/PRELOAD ..............C-12 C.6.1.4 CLAMP................... C-12 C.6.1.5 BYPASS..................C-13 C.6.2 Boundary Scan Register..............C-13 C.6.3 Restrictions ..................C-16 C.6.4 Disabling The IEEE Standard 1149.1A Operation......C-16 C.6.5 MC68040V and MC68EC040V JTAG Electrical Characteristics ..C-17 MOTOROLA M68040 USER’S MANUAL...
Page 884 DC Electrical Specifications .............. C-20 C.7.4 Power Dissipation................C-20 C.7.5 Clock AC Timing Specifications ............C-21 C.7.6 Output AC Timing Specifications ............C-22 C.7.7 Input AC Timing Specifications............C-23 Appendix D M68000 Family Summary Appendix E Floating-Point Emulation (M68040FPSP) Index M68040 USER’S MANUAL MOTOROLA...
Page 885 ATC Entry and Tag Fields ................3-27 3-22 Address Translation Flowchart..............3-32 3-23 MMU Status Interpretation ................3-35 Overview of Internal Caches ................ 4-2 Cache Line Formats ..................4-3 Caching Operation ..................4-4 Cache Control Register ................4-5 MOTOROLA M68040 USER’S MANUAL xvii...
Page 886 7-22 Interrupt Acknowledge Bus Cycle Timing ............ 7-33 7-23 Autovector Interrupt Acknowledge Bus Cycle Timing ........7-34 7-24 Breakpoint Interrupt Acknowledge Bus Cycle Flowchart ......7-35 7-25 Breakpoint Interrupt Acknowledge Bus Cycle Timing ........7-36 xviii M68040 USER’S MANUAL MOTOROLA...
Page 887 Floating-Point Control Register ..............9-4 FPSR Condition Code Byte................9-4 FPSR Quotient Byte ..................9-5 FPSR Exception Status Byte ............... 9-5 FPSR Accrued Exception Byte ..............9-6 Intermediate Result Format................9-12 Rounding Algorithm Flowchart ..............9-14 MOTOROLA M68040 USER’S MANUAL...
Page 888 MC68EC040 Functional Signal Groups ............B-4 MC68EC040 Access Control Register Format ..........B-6 MC68EC040 Initial Power-On Reset Timing..........B-8 MC68EC040 Normal Reset Timing .............. B-9 Clock Input Timing Diagram ................. B-14 Read/Write Timing ..................B-17 Bus Arbitration Timing.................. B-18 M68040 USER’S MANUAL MOTOROLA...
Page 889 Other Signal Timing ..................C-28 C-18 Going into LPSTOP with Arbitration ............. C-29 C-19 LPSTOP no Arbitration, CPU is Master ............C-30 C-20 Exiting LPSTOP with Interrupt..............C-31 C-21 Exiting of LPSTOP with RESET ..............C-31 MOTOROLA M68040 USER’S MANUAL...
Page 890 Interrupt Acknowledge Termination Summary ..........7-31 TA and TEA Assertion Results ..............7-37 M68040 Bus Arbitration States ..............7-48 Exception Vector Assignments ..............8-5 Tracing Control .................... 8-11 Interrupt Levels and Mask Values..............8-12 Exception Priority Groups ................8-19 xxii M68040 USER’S MANUAL MOTOROLA...
Page 891 Bus Encodings During LPSTOP Broadcast Cycle ........C-4 IEEE Standard 1149.1A Instructions............C-12 MC68040 Floating-Point Instructions ............E-2 MC68040FPSP Floating-Point Instructions..........E-3 Support for Data Types and Data Formats ..........E-4 Exception Conditions ................... E-4 MOTOROLA M68040 USER’S MANUAL xxiii...
Page 892 The M68040 family is user object-code compatible with previous M68000 family members and is specifically optimized to reduce the execution time of compiler-generated code. All five processors implement Motorola’s latest HCMOS technology, providing an ideal balance between speed, power, and physical device size.
Page 893 Refer to Appendix B MC68EC040 for specific details on the MC68EC040. Refer to Appendix B MC68EC040 and Appendix C MC68040V and MC68EC040V for specific details on the MC68EC040V. Disregard information concerning the FPU and MMU when reading the following subsections. 1- 2 M68040 USER’S MANUAL MOTOROLA...
Page 894 The M68040 IU pipeline has been expanded from the MC68030 to include effective address calculation (<ea> calculate) and operand fetch ( <ea> fetch) stages with commonly used effective addressing modes. Conditional branches are optimized for the ® UNIX is a registered trademark of AT&T Bell Laboratories. MOTOROLA M68040 USER’S MANUAL 1- 3...
Page 895 The caches improve the overall performance of the system by reducing the number of bus transfers required by the processor to fetch information from memory and by increasing the bus bandwidth available for alternate bus 1- 4 M68040 USER’S MANUAL MOTOROLA...
Page 896 1.6 PROGRAMMING MODEL The MC68040 programming model is separated into two privilege modes: supervisor and user. The S-bit in the status register (SR) indicates the privilege mode that the processor MOTOROLA M68040 USER’S MANUAL 1- 5...
Page 897 The MC68040 user programming model also incorporates the MC68881/MC68882 programming model consisting of eight, 80-bit, floating-point data registers, a floating-point control register, a floating-point status register, and a floating- point instruction address register. 1- 6 M68040 USER’S MANUAL MOTOROLA...
Page 898 DATA TRANSPARENT TRANSLATION REGISTER 0 DTT1 DATA TRANSPARENT TRANSLATION REGISTER 1 ITT0 INSTRUCTION TRANSPARENT TRANSLATION REGISTER 0 ITT1 INSTRUCTION TRANSPARENT TRANSLATION REGISTER 1 MMUSR MMU STATUS REGISTER SUPERVISOR PROGRAMMING MODEL Figure 1-2. Programming Model MOTOROLA M68040 USER’S MANUAL 1- 7...
Page 899 (FPIAR) to locate the floating-point instruction that has caused an exception. Instructions that do not modify the FPIAR can be used to read the FPIAR in the exception handler without changing the previous value. 1- 8 M68040 USER’S MANUAL MOTOROLA...
Page 900 1.8 ADDRESSING CAPABILITIES SUMMARY The M68040 supports the basic addressing modes of the M68000 family. The register indirect addressing modes support postincrement, predecrement, offset, and indexing, which are particularly useful for handling data structures common to sophisticated MOTOROLA M68040 USER’S MANUAL 1- 9...
Page 901 Displacement (d 16 ,PC) Program Counter Indirect with Index 8-Bit Displacement (d 8 ,PC,Xn) Base Displacement (bd,PC,Xn) Program Counter Memory Indirect Postindexed ([bd,PC],Xn,od) Preindexed ([bd,PC,Xn],od) Absolute Data Addressing Short (xxx).W Long (xxx).L Immediate #<xxx> 1- 10 M68040 USER’S MANUAL MOTOROLA...
Page 902 Data register D7–D0, used during update. Dx, Dy Source and destination data registers, respectively. Any Memory Register n. Any Address or Data Register Rx, Ry Any source and destination registers, respectively. Index Register—An, Dn, or suppressed. MOTOROLA M68040 USER’S MANUAL 1- 11...
Page 903 Any Floating-Point Data Register specified as the source or destination, respectively. IC, DC, IC/DC Instruction, Data, or Both Caches MMUSR MMU Status Register Program Counter Any Non Floating-Point Control Register Source Function Code Register Status Register 1- 12 M68040 USER’S MANUAL MOTOROLA...
Page 904 Register Codes General Case. Carry Bit in CCR Condition Codes from CCR Function Code Negative Bit in CCR Undefined, Reserved for Motorola Use. Overflow Bit in CCR Extend Bit in CCR Zero Bit in CCR — Not Affected or Applicable.
Page 905 BRA <label> BSET ~(bit number of Destination) ø Z; BSET Dn,<ea> 1 ø bit number of Destination BSET #<data>,<ea> SP – 4 ø SP; PC ø (SP); PC + d n ø PC BSR <label> 1- 14 M68040 USER’S MANUAL MOTOROLA...
Page 906 Immediate Data ⊕ Destination ø Destination EORI EORI #<data>,<ea> Source ⊕ CCR ø CCR EORI to CCR EORI #<data>,CCR EORI to SR If supervisor state EORI #<data>,SR then Source ⊕ SR ø SR else TRAP MOTOROLA M68040 USER’S MANUAL 1- 15...
Page 907 FMOVEM.X <ea>,Dn FMOVEM 2 FMOVEM.L <list>,<ea> 5 Register List ø Destination FMOVEM.L <ea>,<list> 5 Source ø Register List FMUL 2 Source × FPn ø FPn FMUL.<fmt> <ea>,FPn FMUL.X FPm,FPn FrMUL<fmt> <ea>,FPn 3 FrMUL.X FPm,FPn 3 1- 16 M68040 USER’S MANUAL MOTOROLA...
Page 908 SP – 4 ø SP; PC ø (SP) JSR <ea> Destination Address ø PC <ea> ø An LEA <ea>,An LINK SP – 4 ø SP; An ø (SP) LINK An,d n SP ø An, SP+d ø SP MOTOROLA M68040 USER’S MANUAL 1- 17...
Page 909 32 × 32 ø 64 MULU.L <ea>,Dh–Dl NBCD 0 – (Destination 10 ) – X ø Destination NBCD <ea> 0 – (Destination) ø Destination NEG <ea> NEGX 0 – (Destination) – X ø Destination NEGX <ea> 1- 18 M68040 USER’S MANUAL MOTOROLA...
Page 910 If condition true Scc <ea> then 1s ø Destination else 0s ø Destination STOP If supervisor state STOP #<data> then Immediate Data ø SR; STOP else TRAP Destination – Source ø Destination SUB <ea>,Dn SUB Dn,<ea> MOTOROLA M68040 USER’S MANUAL 1- 19...
Page 911 7. MOVE16 (ax)+,(ay)+ is functionally the same as MOVE16 (ax),(ay)+ when ax = ay. The address register is only incremented once, and the line is copied over itself rather than to the next line. 8. Not available for the MC68EC040 or MC68EC040V. 1- 20 M68040 USER’S MANUAL MOTOROLA...
Page 912 These write- backs to memory can be deferred until the most opportune moment because of the M68040 bus interface. Figure 2-1 illustrates the IU pipeline. MOTOROLA M68040 USER’S MANUAL 2- 1...
Page 913 For memory indirect addressing modes, the <ea> calculate stage initiates an operand fetch from the intermediate indirect memory address, then calculates the final 2- 2 M68040 USER’S MANUAL MOTOROLA...
Page 914 CALCULATE <ea> DATA DATA MEMORY UNIT FETCH PHYSICAL ADDRESS DATA EXECUTE DATA MUX DATA MMU/ CACHE/SNOOP WRITE- CONTROLLER BACK (WB3) CONTROL PUSH SIGNALS BUFFER INTEGER UNIT DATA CACHE Figure 2-2. Write-Back Cycle Block Diagram MOTOROLA M68040 USER’S MANUAL 2- 3...
Page 915 The address registers may be used for word and long-word operations. DATA REGISTERS ADDRESS REGISTERS USER STACK (USP) POINTER PROGRAM COUNTER CONDITION CODE REGISTER Figure 2-3. Integer Unit User Programming Model 2- 4 M68040 USER’S MANUAL MOTOROLA...
Page 916 M68040 are in the supervisor programming model. Thus, all application software is written to run in the user mode and migrates to the M68040 from any M68000 platform without modification. MOTOROLA M68040 USER’S MANUAL 2- 5...
Page 917 SSP references access the MSP when the M-bit is set. The operating system uses the MSP for each task pointing to a task-related area of supervisor data space. This 2- 6 M68040 USER’S MANUAL MOTOROLA...
Page 918 The processor automatically generates function codes to select address spaces for data and programs at the user and supervisor modes. Certain instructions use the SFC and DFC registers to specify the function codes for operations. MOTOROLA M68040 USER’S MANUAL 2- 7...
Page 919 Setting an enable bit enables the associated cache without affecting the state of any lines within the cache. A hardware reset clears the CACR, disabling both caches. 2- 8 M68040 USER’S MANUAL MOTOROLA...
Page 920 • Caching Mode Selected on Page Basis The MMUs completely overlap address translation time with other processing activities when the translation is resident in one of the ATCs. ATC accesses operate in parallel with MOTOROLA M68040 USER'S MANUAL 3- 1...
Page 921 The principal MMU function is to translate logical addresses to physical addresses using translation tables stored in memory. As the MMU receives a logical address from the integer unit, it searches its ATC for the corresponding physical address using the upper 3- 2 M68040 USER'S MANUAL MOTOROLA...
Page 922 ATCs may no longer be valid. A PFLUSH instruction should be executed to flush the ATCs before loading a new root pointer value, if necessary. Figure 3-3 illustrates the format of the 32-bit URP and SRP registers. Bits 8– MOTOROLA M68040 USER'S MANUAL 3- 3...
Page 923 (UPA1 and UPA0) are zero. P—Page Size This bit selects the memory page size. 0 = 4 Kbytes 1 = 8 Kbytes A reset operation does not affect this bit. The bit must be initialized after a reset. 3- 4 M68040 USER'S MANUAL MOTOROLA...
Page 924 UPA0 and UPA1 signals, respectively, if an external bus transfer results from an access. These bits can be programmed by the user to support external addressing, bus snooping, or other applications. MOTOROLA M68040 USER'S MANUAL 3- 5...
Page 925 If the B-bit is set, all other bits are zero. G—Global This bit is set if the G-bit is set in the page descriptor. U1, U0—User Page Attributes These bits are set if corresponding bits in the page descriptor are set. 3- 6 M68040 USER'S MANUAL MOTOROLA...
Page 926 Only a portion of the translation table for the entire logical address space is required to be resident in memory at any time—specifically, only the portion of the table that translates MOTOROLA M68040 USER'S MANUAL 3- 7...
Page 927 23 bits of the appropriate root pointer (URP or SRP) to yield the physical address of a root-level table descriptor. Each of the 128 root-level table descriptors corresponds to a 32-Mbyte block of memory and points to the base of a pointer-level table. 3- 8 M68040 USER'S MANUAL MOTOROLA...
Page 928 An access error due to a system malfunction can require the exception handler to write an error message and terminate the task. MOTOROLA M68040 USER'S MANUAL 3- 9...
Page 929 ATC ENTRY PFA, DF[U1,U0,S,CM,M],WP ABBREVIATIONS: PFA - PAGE FRAME ADDRESS EXIT TABLE SEARCH DF[ ] - DESCRIPTOR FIELD WP - ACCUMULATED WRITE- PROTECTION STATUS ASSIGNMENT OPERATOR Figure 3-9. Detailed Flowchart of Table Search Operation 3- 10 M68040 USER'S MANUAL MOTOROLA...
Page 930 CREATE ATC ENTRY OF ALL BUS TRANSFERS WP – ACCUMULATED WRITE- WITH R-BIT CLEAR PROTECTION STATUS V – LOGICAL "OR" OPERATOR RETURN EXIT TABLE SEARCH – ASSIGNMENT OPERATOR Figure 3-10. Detailed Flowchart of Descriptor Fetch Operation MOTOROLA M68040 USER'S MANUAL 3- 11...
Page 931 Motorola highly recommends that the translation tables be placed in cache-inhibited memory space. Motorola also highly recommends table descriptors must not be left in states that are incoherent to the processor. Future processors may treat these recommendations as mandatory. The following paragraphs apply only to M68040 systems that cannot meet these recommendations.
Page 932 00 = Cachable, Write-through 01 = Cachable, Copyback 10 = Noncachable, Serialized 11 = Noncachable Section 4 Instruction and Data Caches provides detailed information on caching modes, and Section 7 Bus Operation provides information on serialization. MOTOROLA M68040 USER'S MANUAL 3- 13...
Page 933 This bit identifies a page as supervisor only. Only programs operating in the supervisor mode are allowed to access the portion of the logical address space mapped by this descriptor when the S-bit is set. If the bit is clear, both supervisor and user accesses are allowed. 3- 14 M68040 USER'S MANUAL MOTOROLA...
Page 934 When the W-bit is set, a write access or a read-modify-write access to the logical address corresponding to this entry causes an access error exception to be taken. X—Motorola Reserved These bit fields are reserved for future use by Motorola. MOTOROLA M68040 USER'S MANUAL 3- 15...
Page 935 (i.e., the modified indication is maintained only in the single descriptor). The indirection capability also allows the page frame to appear at arbitrarily different addresses in the logical address spaces of each task. 3- 16 M68040 USER'S MANUAL MOTOROLA...
Page 936 PDT field with an indirect encoding (it must be either a resident descriptor or invalid). Otherwise, the descriptor is treated as invalid, and the M68040 creates an ATC entry with a signaled error condition (R-bit in MMUSR is clear). MOTOROLA M68040 USER'S MANUAL 3- 17...
Page 937 Also, the shared area appears at different logical addresses for each task. Figure 3-15 illustrates shared tables in a translation table structure. 3- 18 M68040 USER'S MANUAL MOTOROLA...
Page 938 This determination can be facilitated by using he unused bits in the descriptor to store status information concerning the invalid encoding. The M68040 does not interpret or modify an invalid descriptor’s fields except for the UDT field. This MOTOROLA M68040 USER'S MANUAL 3- 19...
Page 939 UDT = INVALID UDT = INVALID TABLE $7F TABLE $1F NONRESIDENT NONRESIDENT NONRESIDENT (PAGED OR (PAGED OR (PAGED OR UNALLOCATED) UNALLOCATED) UNALLOCATED) ROOT-LEVEL POINTER-LEVEL PAGE-LEVEL TABLES TABLES TABLES Figure 3-16. Translation Table with Nonresident Tables 3- 20 M68040 USER'S MANUAL MOTOROLA...
Page 940 U-bit occurs only if the U-bit was clear. Table 3-1 lists the page descriptor update operations for each combination of U-bit, M-bit, write-protected, and read or write access type. MOTOROLA M68040 USER'S MANUAL 3- 21...
Page 941 Invalidation of the instruction cache line containing the referenced location to maintain cache coherency must precede MOVES accesses that write the instruction address space. The SFC and DFC values and results are listed in Table 3-2. Table 3-2. SFC and DFC Values Results SFC/DFC Value 3- 22 M68040 USER'S MANUAL MOTOROLA...
Page 942 The entire user and supervisor address spaces can be mapped together by loading the same root pointer address into both the SRP and URP registers. MOTOROLA M68040 USER'S MANUAL 3- 23...
Page 943 THIS AREA IS SUPERVISOR ONLY, READ-ONLY THIS AREA IS SUPERVISOR ONLY, READ/WRITE THIS AREA IS SUPERVISOR OR USER, READ-ONLY THIS AREA IS SUPERVISOR OR USER, READ/WRITE Figure 3-18. Logical Address Map with Shared Supervisor and User Address Spaces 3- 24 M68040 USER'S MANUAL MOTOROLA...
Page 944 THIS PAGE SUPERVISOR/USER, READ/WRITE W = 0 S = 0,W = 0 ROOT-LEVEL POINTER-LEVEL PAGE-LEVEL TABLE TABLE TABLE NOTE: X = Don’t care. Figure 3-19. Translation Table Using S-Bit and W-Bit To Set Protection MOTOROLA M68040 USER'S MANUAL 3- 25...
Page 945 PAGE SIZE PA(31–13) SET 0 ENTRY SELECT SET 1 STATUS • • • • • • ENTRY SET 15 LINE SELECT HIT 3 HIT 2 DETECT HIT 1 HIT 0 COMPARATOR Figure 3-20. ATC Organization 3- 26 M68040 USER'S MANUAL MOTOROLA...
Page 946 M68040 suspends the access, initiates a table search to set the M-bit in the page descriptor, and writes over the old ATC entry with the current page descriptor information. The MMU then allows the original write access to be performed. This MOTOROLA M68040 USER'S MANUAL 3- 27...
Page 947 When the ATC does not contain the translation for a logical address, a miss occurs. The MMU aborts the current access and searches the translation tables in memory for the correct translation. If the table search completes without any errors, the MMU stores the 3- 28 M68040 USER'S MANUAL MOTOROLA...
Page 948 The address for the current bus cycle and a TTR address match when the privilege mode and logical base address bits are equal. Each TTR can specify write protection for the block. When write protection is enabled for a block, write or read-modify-write accesses to the block are aborted. MOTOROLA M68040 USER'S MANUAL 3- 29...
Page 949 A-line, illegal, CHK, or unimplemented instruction and the next page is non-resident. Instead, the M68040 attempts to prefetch the next instruction on the missing page, then the ATC access error exception is reported. The stacked PC points to the exceptional 3- 30 M68040 USER'S MANUAL MOTOROLA...
Page 950 MMUs on the next boundary after the signal is negated. The assertion of this signal does not affect the operation of the transparent translation registers or execution of the PFLUSH or PTEST instructions. MOTOROLA M68040 USER'S MANUAL 3- 31...
Page 951 TTR0* [CM] ABORT CYCLE EXIT EXIT TABLE SEARCH OPERATION ATC ENTRY [PA] ATC ENTRY [U1,U0] ATC ENTRY [CM] EXIT * Refers to either instruction or data transparent translation register. Figure 3-22. Address Translation Flowchart 3- 32 M68040 USER'S MANUAL MOTOROLA...
Page 952 MMUSR for the source of the fault. The M68040 MMU instructions use opcodes that are different from those for the corresponding instructions in the MC68030 and MC68851. All MMU opcodes for the MOTOROLA M68040 USER'S MANUAL 3- 33...
Page 953 3-23 can be used to determine the cause of an MMU fault. The PTEST instruction sets the bits in the MMUSR appropriately, and the program can branch to the appropriate code segment for the condition. 3- 34 M68040 USER'S MANUAL MOTOROLA...
Page 954 INDICATED IN STACK RMW ACCESS INDICATED IN FRAME STACK FRAME) NOT MMU BRANCH TO "WRITE NOT MMU VIOLATION" CODE * Refers to either instruction or data transparent translation register. Figure 3-23. MMU Status Interpretation MOTOROLA M68040 USER'S MANUAL 3- 35...
Page 955 (dirty data). Allowing memory pages to be specified as write-through instead of copyback also supports cache coherency. When a processor writes to write-through pages, external MOTOROLA M68040 USER’S MANUAL 4- 1...
Page 956 Note that only the data cache supports dirty cache lines. Figure 4-2 illustrates the instruction cache line format (a) and the data cache line format (b). 4- 2 M68040 USER'S MANUAL MOTOROLA...
Page 957 Consequently, if the accesses span page boundaries, misaligned accesses to peripherals are not possible unless the peripheral can tolerate double reads or writes. MOTOROLA M68040 USER’S MANUAL 4- 3...
Page 958 When a miss occurs and all four lines in the set are valid, the line pointed to by the current counter value is replaced, after which the counter is incremented. 4- 4 M68040 USER'S MANUAL MOTOROLA...
Page 959 The state of the CDIS signal or the cache enable bits in the CACR does not affect the operation of CINV and CPUSH. Both instructions allow operation on a single cache line, all cache lines in a specific page, or an MOTOROLA M68040 USER’S MANUAL 4- 5...
Page 960 When a miss causes a dirty cache line to be selected for replacement, the memory unit places the line in an internal copyback buffer. The replacement line is read into the cache, and writing the dirty cache line back to memory updates memory. 4- 6 M68040 USER'S MANUAL MOTOROLA...
Page 961 4.4 CACHE PROTOCOL The cache protocol for processor and snooped accesses is described in the following paragraphs. In all cases, an external bus transfer will cause a cache line state to change MOTOROLA M68040 USER’S MANUAL 4- 7...
Page 962 The cache line state does not change. A write-through access to a line containing dirty data constitutes a system programming error even if the D-bits for the line are unchanged. This situation can be 4- 8 M68040 USER'S MANUAL MOTOROLA...
Page 963 Invalidate Line Reserved (Snoop Inhibited) Reserved (Snoop Inhibited) The snooping protocol and caching mechanism supported by the M68040 are optimized to support multimaster systems with the M68040 as the single caching master. In systems MOTOROLA M68040 USER’S MANUAL 4- 9...
Page 964 A system programming error occurs when page attributes are changed without flushing the corresponding page from the cache, resulting in cache line states inconsistent with their page definitions. Even with these inconsistencies, the cache is defined and predictable. 4- 10 M68040 USER'S MANUAL MOTOROLA...
Page 965 When a cache line read is initiated, the first cycle attempts to load the line entry corresponding to the instruction half-line or data item requested by the IU. Subsequent transfers are for the remaining entries in the cache line. In the case of a misaligned MOTOROLA M68040 USER’S MANUAL 4- 11...
Page 966 If a cache inhibit or bus error occurs on a replacement line read, a dirty line is restored to the cache from the push buffer. However, the line being replaced is not restored in the cache if it was originally valid and the cache line remains invalid. If the line 4- 12 M68040 USER'S MANUAL MOTOROLA...
Page 967 The instruction and data caches function independently when servicing access requests from the IU. The following paragraphs discuss the operational details for the caches and present state diagrams depicting the cache line state transitions. MOTOROLA M68040 USER’S MANUAL 4- 13...
Page 968 Table 4-3. I3–CINV/CPUSH V1–CPU READ MISS V2–CPU READ HIT I1-CPU READ MISS INVALID VALID V3–CINV/CPUSH V5–SNOOP READ HIT V6–SNOOP WRITE HIT Figure 4-5. Instruction-Cache Line State Diagram 4- 14 M68040 USER'S MANUAL MOTOROLA...
Page 969 Transitions are labeled with a capital letter, indicating the previous state, followed by a number indicating the specific case listed in Table 4-4. MOTOROLA M68040 USER’S MANUAL 4- 15...
Page 970 D6—CPU WRITE HIT/WT WT—WRITE-THROUGH MODE D9—SNOOP READ HIT/LEAVE DIRTY CB—COPYBACK MODE D12—SNOOP WRITE HIT/SINK DATA & SIZE = LINE SNOOP OPERATION INDICATES: READ OR WRITE / SNOOP CONTROL ENCODING Figure 4-6. Data-Cache Line State Diagram 4- 16 M68040 USER'S MANUAL MOTOROLA...
Page 971 — Leave Dirty) current state. NOTE: Dirty state transitions D4 and D6 are the result of a system programming error and should be avoided even though they are technically valid. MOTOROLA M68040 USER’S MANUAL 4- 17...
Page 972 Alternate Master Write Hit I13 Not Possible V13 No action; go to invalid D13 No action; go to invalid (Snoop Control = 01 state. state. — Sink Data and Size = Line) 4- 18 M68040 USER'S MANUAL MOTOROLA...
Page 973 (FPU). For the MC68EC040 and MC68EC040V only, ignore all references to the memory management unit (MMU). Some pin names are different on these parts; please refer to the appropriate appendix in the back of this book for more information. MOTOROLA M68040 USER’S MANUAL 5- 1...
Page 974 Used during an interrupt acknowledge transfer to request internal generation AVEC of the vector number. Processor Status PST3–PST0 Indicates internal processor status. Bus Clock BCLK Clock input used to derive all bus signal timing. 5- 2 M68040 USER’S MANUAL MOTOROLA...
Page 975 2. This signal is not available on the MC68EC040 and the MC68EC040V. 3. These signals are different on power-up for the MC68LC040 and MC68EC040. 4. These signals are not available on the MC68040V and MC68EC040V. MOTOROLA M68040 USER’S MANUAL 5- 3...
Page 976 The level on CDIS can select a multiplexed bus mode during processor reset, which allows the address bus and data bus to be physically tied together for multiplexed bus 5- 4 M68040 USER’S MANUAL MOTOROLA...
Page 977 The acknowledge access (TT1 = 1 and TT0 = 1) is used for both interrupt and breakpoint acknowledge transfers, and for LPSTOP broadcast cycles on the MC68040V and MC68EC040V. Table 5-2. Transfer-Type Encoding Transfer Type Normal Access MOVE16 Access Alternate Logical Function Code Access Acknowledge Access MOTOROLA M68040 USER’S MANUAL 5- 5...
Page 978 These three-state outputs indicate which line in the set of four data cache lines is being accessed for normal push and line data read accesses. TLNx signals are undefined for all other accesses to instruction space and are placed in a high-impedance state when the processor relinquishes the bus. 5- 6 M68040 USER’S MANUAL MOTOROLA...
Page 979 When the M68040 is not the bus master, the LOCKE signal is set to a high-impedance state. LOCKE drives high before MOTOROLA M68040 USER’S MANUAL 5- 7...
Page 980 (dirty) data in the M68040 caches. 5.4.4 Transfer Error Acknowledge ( The current slave asserts this input signal to indicate an error condition for the bus transaction. When asserted with TA, this signal indicates that the processor should retry 5- 8 M68040 USER’S MANUAL MOTOROLA...
Page 981 It updates its caches on a write or supplies data to the alternate bus master on a read. MI is negated when the M68040 is the bus master. During a snoop MOTOROLA M68040 USER’S MANUAL 5- 9...
Page 982 (CDIS high) or multiplexed bus mode (CDIS low). Refer to Section 4 Instruction and Data Caches for information about the caches and to Section 7 Bus Operation for information about the multiplexed bus mode. Refer to Appendix E 5- 10 M68040 USER’S MANUAL MOTOROLA...
Page 983 TLN1–TLN0, TM2–TM0, TT1–TT0, UPA1–UPA0 Miscellaneous Control Signals: IPL0 BB, BR , IPEND, MI, PST3–PST0, RSTO , TA, TDO, TIP , TS NOTE: High input level = small buffers enabled; low input level = large buffers enabled. MOTOROLA M68040 USER’S MANUAL 5- 11...
Page 984 The encodings 1, 2, 3, 9, A, and B belong to the first class of PSTx encoding. This class indicates that the instruction is in its last instruction execution stage. These encodings exist for only one BCLK period per instruction and are mutually exclusive. 5- 12 M68040 USER’S MANUAL MOTOROLA...
Page 985 All other instructions and conditions end with the ‘end current instruction’ encoding. For instance, if the processor is running back-to-back single clock instructions, the encoding ‘end current instruction’ remains asserted for as many clock cycles as instructions. MOTOROLA M68040 USER’S MANUAL 5- 13...
Page 986 This input signal is used in DLE mode to latch the input data bus on read transfers. DLE mode can be used to support asynchronous memory interfaces by allowing the interface to specify when data should be latched instead of requiring data to be valid on the rising edge of BCLK. 5- 14 M68040 USER’S MANUAL MOTOROLA...
Page 987 The V and ground connections are grouped to supply adequate current to the various sections of the processor. Section 12 Ordering Information and Mechanical Data describes the groupings of V and ground connections. MOTOROLA M68040 USER’S MANUAL 5- 15...
Page 988 Input — Transfer Cache Inhibit Input — Transfer Error Acknowledge Input — Transfer in Progress Output Transfer Line Number TLN1, TLN0 Output High Transfer Modifier TM2–TM0 Output High Transfer Size SIZ1, SIZ0 Input/Output High 5- 16 M68040 USER’S MANUAL MOTOROLA...
Page 989 — NOTES: 1. This signal is not available on the MC68LC040 and MC68EC040. 2. These signals are different on power-up for the MC68LC040 and MC68EC040. 3. This signal is not available on the MC68EC040. MOTOROLA M68040 USER’S MANUAL 5- 17...
Page 990 Certain precautions must be observed to ensure that this logic does not interfere with system operation. Refer to 6.5 Disabling the IEEE Standard 1149.1A Operation. MOTOROLA M68040 USER’S MANUAL 6- 1...
Page 991 The boundary scan register links all device signal pins into the instruction shift register. TEST DATA REGISTERS 184-BIT BOUNDARY SCAN REGISTER BYPASS LATCHED DECODER 3-BIT INSTRUCTION SHIFT REGISTER TRST Figure 6-1. M68040 Test Logic Block Diagram 6- 2 M68040 USER’S MANUAL MOTOROLA...
Page 992 6.2.1 EXTEST The external test instruction (EXTEST) selects the 184-bit boundary scan register. This instruction also activates two internal functions that are intended to protect the device from potential damage while performing boundary scan operations. MOTOROLA M68040 USER’S MANUAL 6- 3...
Page 993 EXTEST instruction. 6.2.4 DRVCTL.T The DRVCTL.T instruction is a Motorola public instruction that provides the ability to select one of two output drivers on a pin-by-pin basis. It is intended for use with EXTEST or SHUTDOWN to provide an IEEE-compatible environment to select the output drivers for board-level test environments.
Page 994 The test logic controls the I/O state, and the bypass register is selected. 6.2.6 PRIVATE Motorola reserves this instruction for manufacturing use. The instruction does not change pin I/O as defined for system operation. 6.2.7 DRVCTL.S The DRVCTL.S instruction controls the output driver selection on a pin-by-pin basis. This instruction allows data in the boundary scan register to select the output driver during the update-DR state when the system logic has control of the signal I/O directions and levels.
Page 995 IO.Ctl, that are associated with a boundary scan register bit. All boundary scan output cells capture the logic level of the device output latch during the capture-DR state. Figures 6-3 through 6-5 illustrate these three cell types. Figure 6-6 illustrates the general arrangement of these cells. 6- 6 M68040 USER’S MANUAL MOTOROLA...
Page 996 CLOCK DR UPDATE DR2 UPDATE DR1 LAST (DRVCTL.X) (DRVCTL.X) CELL Figure 6-3. Output Latch Cell (O.Latch) TO NEXT CELL INPUT SYSTEM LOGIC CLOCK DR FROM SHIFT DR LAST CELL Figure 6-4. Input Pin Cell (I.Pin) MOTOROLA M68040 USER’S MANUAL 6- 7...
Page 997 CELL Figure 6-5. Output Control Cells (IO.Ctl) TO NEXT CELL OUTPUT I/O.CTL ENABLE INPUT OUTPUT O.LATCH DATA INPUT I.PIN DATA FROM TO NEXT LAST CELL PIN PAIR Figure 6-6. General Arrangement of Bidirectional Pins 6- 8 M68040 USER’S MANUAL MOTOROLA...
Page 998 I/O indicates a bidirectional pin. The last column lists the name of the associated control bit of the boundary scan register for three-state output and bidirectional pins. The boundary scan description language (BSDL) type for each cell can be found in note 1. MOTOROLA M68040 USER’S MANUAL 6- 9...
Page 999 I/O 2 I.Pin io.ab O.Latch io.db I/O 2 I/O 2 O.Latch io.ab O.Latch io.db I/O 2 I.Pin io.ab O.Latch io.db I/O 2 I/O 2 O.Latch io.ab O.Latch io.db I/O 2 I.Pin io.ab O.Latch io.db 6- 10 M68040 USER’S MANUAL MOTOROLA...
Page 1000 O.Latch SIZ0 io.0 I.Pin io.db I.Pin SIZ0 io.0 I/O 2 I.Pin io.db O.Latch io.0 I.Pin io.db I.Pin R/ W io.0 TS-Output 2 I.Pin io.db O.Latch io.1 LOCKE I/O 2 I.Pin io.db O.Latch SIZ1 io.0 MOTOROLA M68040 USER’S MANUAL 6- 11...
Page 1001 After any of the four instructions has been properly entered, these instructions can be executed in any order without a time-domain clocking restriction. Entering any instruction other than one of these four requires that the system clocks be 6- 12 M68040 USER’S MANUAL MOTOROLA...

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