ST STM32L4+ Series Reference Manual page 1640

Tamper and backup registers (TAMP) applied to STM32L4P5xx and STM32L4Q5xx only
48.6.2 TAMP control register 2 (TAMP_CR2)
Address offset: 0x04
Backup domain reset value: 0x0000 0000
System reset: not affected
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:27 Reserved, must be kept at reset value.
Bit 26 TAMP3TRG: Active level for tamper 3 input
Bit 25 TAMP2TRG: Active level for tamper 2 input
Bit 24 TAMP1TRG: Active level for tamper 1 input
Bit 23 BKERASE: Backup registers erase
Bits 22:19 Reserved, must be kept at reset value.
Bit 18 TAMP3MSK: Tamper 3 mask
1640/2301
28 27 26 25
TAMP3 TAMP2
Res.
TRG TRG
rw rw
12 11 10 9
Res. Res. Res.
0: If TAMPFLT ≠ 00 Tamper 3 input staying low triggers a tamper detection event.
If TAMPFLT = 00 Tamper 3 input rising edge and high level triggers a tamper detection
event.
1: If TAMPFLT ≠ 00 Tamper 3 input staying high triggers a tamper detection event.
If TAMPFLT = 00 Tamper 3 input falling edge and low level triggers a tamper detection
event.
0: If TAMPFLT ≠ 00 Tamper 2 input staying low triggers a tamper detection event.
If TAMPFLT = 00 Tamper 2 input rising edge and high level triggers a tamper detection
event.
1: If TAMPFLT ≠ 00 Tamper 2 input staying high triggers a tamper detection event.
If TAMPFLT = 00 Tamper 2 input falling edge and low level triggers a tamper detection
event.
0: If TAMPFLT ≠ 00 Tamper 1 input staying low triggers a tamper detection event.
If TAMPFLT = 00 Tamper 1 input rising edge and high level triggers a tamper detection
event.
1: If TAMPFLT ≠ 00 Tamper 1 input staying high triggers a tamper detection event.
If TAMPFLT = 00 Tamper 1 input falling edge and low level triggers a tamper detection
event.
Writing '1' to this bit reset the backup registers. Writing 0 has no effect. This bit is always
read as 0.
0: Tamper 3 event generates a trigger event and TAMP3F must be cleared by software to
allow next tamper event detection.
1: Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by
hardware. The backup registers are not erased.
The tamper 3 interrupt must not be enabled when TAMP3MSK is set.
24 23 22
TAMP1 BK
Res.
TRG ERASE
w
rw
8 7 6
Res. Res. Res.
RM0432 Rev 6
21 20 19 18
TAMP3
Res. Res. Res.
MSK
rw
5 4 3 2
TAMP3
Res. Res. Res.
NOER
rw
RM0432
17 16
TAMP2 TAMP1
MSK MSK
rw rw
1 0
TAMP2 TAMP1
NOER NOER
rw rw