ST STM32L4+ Series Reference Manual page 1645

RM0432 Tamper and backup registers (TAMP) applied to STM32L4P5xx and STM32L4Q5xx only
48.6.7 TAMP status clear register (TAMP_SCR)
Address offset: 0x3C
System reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 Reserved, must be kept at reset value.
Bit 22 Reserved, must be kept at reset value.
Bit 21 Reserved, must be kept at reset value.
Bit 20 Reserved, must be kept at reset value.
Bit 19 Reserved, must be kept at reset value.
Bit 18 Reserved, must be kept at reset value.
Bit 17 Reserved, must be kept at reset value.
Bit 16 Reserved, must be kept at reset value.
Bits 15:3 Reserved, must be kept at reset value.
Bit 2 CTAMP3F: Clear TAMP3 detection flag
Bit 1 CTAMP2F: Clear TAMP2 detection flag
Bit 0 CTAMP1F: Clear TAMP1 detection flag
48.6.8 TAMP backup x register (TAMP_BKPxR)
Address offset: 0x100 + 0x04 * x, (x = 0 to 31)
Backup domain reset value: 0x0000 0000
System reset: not affected
31 30 29
rw rw rw
15 14 13
rw rw rw
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
Writing 1 in this bit clears the TAMP3F bit in the TAMP_SR register.
Writing 1 in this bit clears the TAMP2F bit in the TAMP_SR register.
Writing 1 in this bit clears the TAMP1F bit in the TAMP_SR register.
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
24 23 22
BKP[31:16]
rw rw rw
8 7 6
BKP[15:0]
rw rw rw
RM0432 Rev 6
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
CTAMP
Res. Res. Res.
3F
w
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw w
17 16
Res. Res.
1 0
CTAMP CTAMP
2F 1F
w w
17 16
rw rw
1 0
rw rw
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