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RM0432
Tamper and backup registers (TAMP) applied to STM32L4P5xx and STM32L4Q5xx only
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 Reserved, must be kept at reset value.
Bit 22 Reserved, must be kept at reset value.
Bit 21 Reserved, must be kept at reset value.
Bit 20 Reserved, must be kept at reset value.
Bit 19 Reserved, must be kept at reset value.
Bit 18 Reserved, must be kept at reset value.
Bit 17 Reserved, must be kept at reset value.
Bit 16 Reserved, must be kept at reset value.
Bits 15:3 Reserved, must be kept at reset value.
Bit 2 TAMP3IE: Tamper 3 interrupt enable
Bit 1 TAMP2IE: Tamper 2 interrupt enable
Bit 0 TAMP1IE: Tamper 1 interrupt enable
48.6.5
TAMP status register (TAMP_SR)
Address offset: 0x30
Backup domain reset value: 0x0000 0000
System reset: not affected
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 Reserved, must be kept at reset value.
Bit 22 Reserved, must be kept at reset value.
Bit 21 Reserved, must be kept at reset value.
Bit 20 Reserved, must be kept at reset value.
Bit 19 Reserved, must be kept at reset value.
Bit 18 Reserved, must be kept at reset value.
Bit 17 Reserved, must be kept at reset value.
0: Tamper 3 interrupt disabled.
1: Tamper 3 interrupt enabled..
0: Tamper 2 interrupt disabled.
1: Tamper 2 interrupt enabled.
0: Tamper 1 interrupt disabled.
1: Tamper 1 interrupt enabled.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0432 Rev 6
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
TAMP
Res.
Res.
Res.
3F
r
17
16
Res.
Res.
1
0
TAMP
TAMP
2F
1F
r
r
1643/2301
1647
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