ST STM32L4+ Series Reference Manual page 1600

Real-time clock (RTC) applied to STM32L4P5xx and STM32L4Q5xx only
RTC register access
The RTC registers are 32-bit registers. The APB interface introduces 2 wait-states in RTC
register accesses except on read accesses to calendar shadow registers when BYPSHAD
= 0.
RTC register write protection
After system reset, the RTC registers are protected against parasitic write access by the
DBP bit in the power control peripheral (refer to the PWR power control section). DBP bit
must be set in order to enable RTC registers write access.
After Backup domain reset, some of the RTC registers are write-protected: RTC_TR,
RTC_DR, RTC_PRER, RTC_CALR, RTC_SHIFTR, the bits INIT, BIN and BCDU in
RTC_ICSR and the bits FMT, SUB1H, ADD1H, REFCKON in RTC_CR.
The following steps are required to unlock the write protection on the protected RTC
registers.
1. Write 0xCA into the RTC_WPR register.
2. Write 0x53 into the RTC_WPR register.
Writing a wrong key reactivates the write protection.
The protection mechanism is not affected by system reset.
Calendar initialization and configuration
To program the initial time and date calendar values, including the time format and the
prescaler configuration, the following sequence is required:
1. Set INIT bit to 1 in the RTC_ICSR register to enter initialization mode. In this mode, the
calendar counter is stopped and its value can be updated.
2. Poll INITF bit of in the RTC_ICSR register. The initialization phase mode is entered
when INITF is set to 1.
If LPCAL=0: INITF is set around 2 RTCCLK cycles after INIT bit is set.
If LPCAL=1: INITF is set up to 2 ck_apre cycle after INIT bit is set.
3. To generate a 1 Hz clock for the calendar counter, program both the prescaler factors
in RTC_PRER register, plus BIN and BCDU in the RTC_ICSR register.
4. Load the initial time and date values in the shadow registers (RTC_TR and RTC_DR),
and configure the time format (12 or 24 hours) through the FMT bit in the RTC_CR
register.
5. Exit the initialization mode by clearing the INIT bit. The actual calendar counter value is
then automatically loaded.
If LPCAL=0: the counting restarts after 4 RTCCLK clock cycles.
If LPCAL=1: the counting restarts after up to 2 RTCCLK + 1 ck_apre.
When the initialization sequence is complete, the calendar starts counting. The RTC_SSR
content is initialized with
•
PREDIV_S in BCD mode (BIN=00)
•
0xFFFF FFFF in binary or mixed (BCD-binary) modes (BIN=01, 10 or 11).
In BCD mode, RTC_SSR contains the value of the synchronous prescaler counter. This
allows one to calculate the exact time being maintained by the RTC down to a resolution of
1 / (PREDIV_S + 1) seconds. As a consequence, the resolution can be improved by
1600/2301 RM0432 Rev 6
RM0432