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Tamper and backup registers (TAMP) applied to STM32L4P5xx and STM32L4Q5xx only
Bit 16 Reserved, must be kept at reset value.
Bits 15:3 Reserved, must be kept at reset value.
Bit 2 TAMP3F: TAMP3 detection flag
Bit 1 TAMP2F: TAMP2 detection flag
Bit 0 TAMP1F: TAMP1 detection flag
48.6.6
TAMP masked interrupt status register (TAMP_MISR)
Address offset: 0x34
Backup domain reset value: 0x0000 0000
System reset: not affected
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 Reserved, must be kept at reset value.
Bit 22 Reserved, must be kept at reset value.
Bit 21 Reserved, must be kept at reset value.
Bit 20 Reserved, must be kept at reset value.
Bit 19 Reserved, must be kept at reset value.
Bit 18 Reserved, must be kept at reset value.
Bit 17 Reserved, must be kept at reset value.
Bit 16 Reserved, must be kept at reset value.
Bits 15:3 Reserved, must be kept at reset value.
Bit 2 TAMP3MF: TAMP3 interrupt masked flag
Bit 1 TAMP2MF: TAMP2 interrupt masked flag
Bit 0 TAMP1MF: TAMP1 interrupt masked flag
1644/2301
This flag is set by hardware when a tamper detection event is detected on the TAMP3 input.
This flag is set by hardware when a tamper detection event is detected on the TAMP2 input.
This flag is set by hardware when a tamper detection event is detected on the TAMP1 input.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
This flag is set by hardware when the tamper 3 interrupt is raised.
This flag is set by hardware when the tamper 2 interrupt is raised.
This flag is set by hardware when the tamper 1 interrupt is raised.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0432 Rev 6
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
TAMP
Res.
Res.
Res.
3MF
r
RM0432
17
16
Res.
Res.
1
0
TAMP
TAMP
2MF
1MF
r
r
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