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RM0432
Tamper and backup registers (TAMP) applied to STM32L4P5xx and STM32L4Q5xx only
48.6.1
TAMP control register 1 (TAMP_CR1)
Address offset: 0x00
Backup domain reset value: 0xFFFF 0000
System reset: not affected
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 Reserved, must be kept at reset value.
Bit 22 Reserved, must be kept at reset value.
Bit 21 Reserved, must be kept at reset value.
Bit 20 Reserved, must be kept at reset value.
Bit 19 Reserved, must be kept at reset value.
Bit 18 Reserved, must be kept at reset value.
Bit 17 Reserved, must be kept at reset value.
Bit 16 Reserved, must be kept at reset value.
Bits 15:3 Reserved, must be kept at reset value.
Bit 2 TAMP3E: Tamper detection on TAMP_IN3 enable
Bit 1 TAMP2E: Tamper detection on TAMP_IN2 enable
Bit 0 TAMP1E: Tamper detection on TAMP_IN1 enable
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
0: Tamper detection on TAMP_IN3 is disabled.
1: Tamper detection on TAMP_IN3 is enabled.
0: Tamper detection on TAMP_IN2 is disabled.
1: Tamper detection on TAMP_IN2 is enabled.
0: Tamper detection on TAMP_IN1 is disabled.
1: Tamper detection on TAMP_IN1 is enabled.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0432 Rev 6
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
TAMP3
Res.
Res.
Res.
E
rw
17
16
Res.
Res.
1
0
TAMP2
TAMP1
E
E
rw
rw
1639/2301
1647
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