ST STM32L4+ Series Reference Manual page 1605

RM0432
Smooth calibration mechanism
The smooth calibration register (RTC_CALR) specifies the number of ck_cal clock cycles to
be masked during the calibration cycle:
•
Setting the bit CALM[0] to 1 causes exactly one pulse to be masked during the
calibration cycle.
• Setting CALM[1] to 1 causes two additional cycles to be masked
•
Setting CALM[2] to 1 causes four additional cycles to be masked
• and so on up to CALM[8] set to 1 which causes 256 clocks to be masked.
Note: CALM[8:0] (RTC_CALR) specifies the number of ck_cal pulses to be masked during the
calibration cycle. Setting the bit CALM[0] to 1 causes exactly one pulse to be masked during
the calibration cycle at the moment when cal_cnt[19:0] is 0x80000; CALM[1] = 1 causes two
other cycles to be masked (when cal_cnt is 0x40000 and 0xC0000); CALM[2] = 1 causes
four other cycles to be masked (cal_cnt = 0x20000/0x60000/0xA0000/ 0xE0000); and so on
up to CALM[8] = 1 which causes 256 clocks to be masked (cal_cnt = 0xXX800).
While CALM allows the RTC frequency to be reduced by up to 487.1 ppm with fine
resolution, the bit CALP can be used to increase the frequency by 488.5 ppm. Setting CALP
to 1 effectively inserts an extra ck_cal pulse every 2
clocks are added during every calibration cycle.
Using CALM together with CALP, an offset ranging from -511 to +512 ck_cal cycles can be
added during the calibration cycle, which translates to a calibration range of -487.1 ppm to
+488.5 ppm with a resolution of about 0.954 ppm.
The formula to calculate the effective calibrated frequency (F
(F
RTCCLK
F
CAL
Caution: PREDIV_A must be greater or equal to 3.
Calibration when PREDIV_A < 3
The CALP bit can not be set to 1 when the asynchronous prescaler value (PREDIV_A bits in
RTC_PRER register) is less than 3. If CALP was already set to 1 and PREDIV_A bits are
set to a value less than 3, CALP is ignored and the calibration operates as if CALP was
equal to 0.
It is however possible to perform a calibration with PREDIV_A less than 3 in BCD mode, the
synchronous prescaler value (PREDIV_S) should be reduced so that each second is
accelerated by 8 ck_cal clock cycles, which is equivalent to adding 256 clock cycles every
calibration cycle. As a result, between 255 and 256 clock pulses (corresponding to a
calibration range from 243.3 to 244.1 ppm) can effectively be added during each calibration
cycle using only the CALM bits.
With a nominal RTCCLK frequency of 32768 Hz, when PREDIV_A equals 1 (division factor
of 2), PREDIV_S should be set to 16379 rather than 16383 (4 less). The only other
interesting case is when PREDIV_A equals 0, PREDIV_S should be set to 32759 rather
than 32767 (8 less).
If PREDIV_S is reduced in this way, the formula given the effective frequency of the
calibrated input clock is as follows:
F = F
CAL
Real-time clock (RTC) applied to STM32L4P5xx and STM32L4Q5xx only
) is as follows:
= F x [1 + (CALP x 512 - CALM) / (2
RTCCLK
x [1 + (256 - CALM) / (2
RTCCLK
11
20
20
+ CALM - 256)]
RM0432 Rev 6
ck_cal cycles, which means that 512
) given the input frequency
CAL
+ CALM - CALP x 512)]
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