ST STM32L4+ Series Reference Manual page 1596

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Real-time clock (RTC) applied to STM32L4P5xx and STM32L4Q5xx only

OSEL[1:0] bits

output enable)

01 or 10 or 11

Clock and prescalers

The RTC clock source (RTCCLK) is selected through the clock controller among the LSE

clock, the LSI oscillator clock, and the HSE clock. For more information on the RTC clock

source configuration, refer to "Reset and clock control (RCC)".

BCD mode (BIN=00)

A programmable prescaler stage generates a 1 Hz clock which is used to update the

calendar. To minimize power consumption, the prescaler is split into 2 programmable

prescalers (see

A 7-bit asynchronous prescaler configured through the PREDIV_A bits of the

RTC_PRER register.

A 15-bit synchronous prescaler configured through the PREDIV_S bits of the

RTC_PRER register.

When both prescalers are used, it is recommended to configure the asynchronous prescaler

to a high value to minimize consumption.

The asynchronous prescaler division factor is set to 128, and the synchronous division

factor to 256, to obtain an internal clock frequency of 1 Hz (ck_spre) with an LSE frequency

of 32.768 kHz.

The minimum division factor is 1 and the maximum division factor is 2

This corresponds to a maximum input frequency of around 4 MHz.

is given by the following formula:

The ck_apre clock is used to clock the binary RTC_SSR subseconds downcounter. When it

reaches 0, RTC_SSR is reloaded with the content of PREDIV_S.

Table 322. RTC_OUT mapping

COE bit (CALIB

output enable)

Figure 457: RTC block

RM0432 Rev 6

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