ST STM32L4+ Series Reference Manual page 1614

Real-time clock (RTC) applied to STM32L4P5xx and STM32L4Q5xx only
Bit 3 SHPF: Shift operation pending
Bit 2 WUTWF: Wakeup timer write flag
Bits 1:0 Reserved, must be kept at reset value.
47.6.5 RTC prescaler register (RTC_PRER)
This register must be written in initialization mode only. The initialization must be performed
in two separate write accesses. Refer to
page 1600.
This register is write protected. The write access procedure is described in
write protection on page
Address offset: 0x10
Backup domain reset value: 0x007F 00FF
System reset: not affected
31 30 29
Res. Res. Res. Res.
15 14 13
Res.
rw rw
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:16 PREDIV_A[6:0]: Asynchronous prescaler factor
Bit 15 Reserved, must be kept at reset value.
Bits 14:0 PREDIV_S[14:0]: Synchronous prescaler factor
1614/2301
This flag is set by hardware as soon as a shift operation is initiated by a write to the
RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has
been executed. Writing to the SHPF bit has no effect.
0: No shift operation is pending
1: A shift operation is pending
This bit is set by hardware when WUT value can be changed, after the WUTE bit has been
set to 0 in RTC_CR.
It is cleared by hardware in initialization mode.
0: Wakeup timer configuration update not allowed except in initialization mode
1: Wakeup timer configuration update allowed
1600.
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
This is the asynchronous division factor:
ck_apre frequency = RTCCLK frequency/(PREDIV_A+1)
This is the synchronous division factor:
ck_spre frequency = ck_apre frequency/(PREDIV_S+1)
Calendar initialization and configuration on
24 23 22
Res. Res.
rw
8 7 6
PREDIV_S[14:0]
rw rw rw
RM0432 Rev 6
RTC register
21 20 19 18
PREDIV_A[6:0]
rw rw rw rw
5 4 3 2
rw rw rw rw
RM0432
17 16
rw rw
1 0
rw rw