Motorola PowerQUICC II MPC8280 Series Reference Manual page 284

Signal Descriptions
Timing Comments Assertion/Negation—The same as the data bus.
7.2.7.2.2 Data Bus Parity (DP[0–7])—Input
Following are the state meaning and timing comments for the DP input signals.
State Meaning
Timing Comments Assertion/Negation—The same as D[0–63].
7.2.8 Data Transfer Termination Signals
Data termination signals are required after each data beat in a data transfer. Note that in a
single-beat transaction that is not a port-size transfer, the data termination signals also
indicate the end of the tenure. In burst or port size accesses, the data termination signals
apply to individual beats and indicate the end of the tenure only after the final data beat. For
a detailed description of how these signals interact, see Section 8.5, "Data Tenure
Operations."
7.2.8.1 Transfer Acknowledge (TA)
The transfer acknowledge (TA) signal is both input and output on the MPC8280.
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including the parity bit, are driven high. The signal assignments are
listed in Table 7-2.
Table 7-2. DP[0–7] Signal Assignments
Signal Name Data Bus Signal Assignments
DP0
DP1
DP2
DP3
DP4
DP5
DP6
DP7
High Impedance—The same as the data bus.
Asserted/Negated—Represents odd parity for each byte of read data.
Parity is checked on all data byte lanes, regardless of the size of the
transfer. Detected even parity causes a checkstop if data parity errors
are enabled in the BCS[PAR_EN].
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D[0–7]
D[8–15
D[16–23]
D[24–31]
D[32–39]
D[40–47]
D[48–55]
D[56–63]
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