Motorola PowerQUICC II MPC8280 Series Reference Manual page 286

Signal Descriptions
Timing Comments Assertion—Depends on whether or not the PCI controller can
7.2.8.2 Transfer Error Acknowledge (TEA)
The transfer error acknowledge (TEA) signal is both input and output on the MPC8280.
7.2.8.2.1 Transfer Error Acknowledge (TEA)—Input
Following are the state meaning and timing comments for the TEA input signal.
State Meaning
Timing Comments Assertion—May be asserted while DBB is asserted and for the cycle
7.2.8.2.2 Transfer Error Acknowledge (TEA)—Output
Following are the state meaning and timing comments for the TEA output.
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Negated—Indicates that master must extend the current data beat
(insert wait states) until data can be provided or accepted by the
MPC8280.
initiate 60x bus global transactions when the address retry
mechanism is in use:
PCI controller is not used or cannot initiate global
transactions—Assertion must occur at least one cycle
following AACK for the current transaction; occurs on the
clock in which the current data transfer can be completed.
PCI controller can initiate global transactions—Assertion must
occur at least one clock cycle following AACK for the
current transaction and at least one clock cycle after ARTRY
can be asserted.
Negation—Occurs after the clock cycle of the final (or only) data
beat of the transfer. For a burst transfer, TA may be negated between
beats to insert one or more wait states before the completion of the
next beat.
Asserted—Indicates that a bus error occurred. The assertion of TEA
causes the negation/high impedance of DBB in the next clock cycle.
However, data entering the MPC8280 internal memory resources
such as GPRs or caches are not invalidated.
Negated—Indicates that no bus error was detected.
after is TA is asserted during a read operation. TEA should be
asserted for one cycle only.
Negation—TEA must be negated no later than the negation of DBB.
MPC8280 PowerQUICC II Family Reference Manual
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