Motorola PowerQUICC II MPC8280 Series Reference Manual page 305

Table 8-7. Unaligned Data Transfer Example (4-Byte Example) (continued)
Program Size of
Word (4 bytes)
Misaligned—1st access
2nd access
Misaligned—1st access
2nd access
Misaligned—1st access
2nd access
1
A: Byte lane used
2
—: Byte lane not used
8.4.3.6 Effect of Port Size on Data Transfers
The MPC8280 can transfer operands through its 64-bit data port. If the transfer is controlled
by the internal memory controller, the MPC8280 can support 8-, 16-, 32-, and 64-bit data
port sizes as demonstrated in Figure 8-6. The bus requires that the portion of the data bus
used for a transfer to or from a particular port size be fixed. A 64-bit port must reside on
data bus bits D[0–63], a 32-bit port must reside on bits D[0–31], a 16-bit port must reside
on bits D[0–15], and an 8-bit port must reside on bits D[0–7]. The MPC8280 always tries
to transfer the maximum amount of data on all bus cycles: for a word operation, it always
assumes the port is 64 bits wide when beginning the bus cycle; for burst and extended byte
cycles, a 64-bit bus is assumed.
Figure 8-6. shows the device connections on the data bus. Table 8-8 lists the bytes required
on the data bus for read cycles.
MOTOROLA
Freescale Semiconductor, Inc.
TSIZ[1–3] A[29–31]
0 1 1 1 0 1
0 0 1 0 0 0
0 1 0 1 1 0
0 1 0 0 0 0
0 0 1 1 1 1
0 1 1 0 0 0
Chapter 8. The 60x Bus
For More Information On This Product,
Go to: www.freescale.com
Address Tenure Operations
Data Bus Byte Lanes
D0... ...D31
B0 B1 B2 B3
— — — —
A — — —
— — — —
A A — —
— — — —
A A A —
D32... ...D63
B4 B5 B6 B7
— A A A
— — — —
— — A A
— — — —
— — — A
— — — —
8-17