Motorola PowerQUICC II MPC8280 Series Reference Manual page 271

7.2 Signal Descriptions
This section describes individual MPC8280 60x signals, grouped according to Figure 7-1.
Note that the following sections briefly summarize signal functions. Chapter 8, "The 60x
Bus," describes many of these signals in greater detail, both in terms of their function and
how groups of signals interact.
7.2.1 Address Bus Arbitration Signals
The address arbitration signals are a collection of input and output signals devices use to
request address bus mastership, recognize when the request is granted, and indicate to other
devices when mastership is granted. For a detailed description of how these signals interact,
see Section 8.4.1, "Address Arbitration."
Bus arbitration signals have no meaning in internal-only mode.
7.2.1.1 Bus Request (BR)—Output
The bus request (BR) signal is both an input and an output signal on the MPC8280.
7.2.1.1.1 Address Bus Request (BR)—Output
Following are the state meaning and timing comments for the BR signal output.
State Meaning
Timing Comments Assertion—May occur on any cycle; does not occur if the MPC8280
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Asserted—Indicates that MPC8280 is requesting mastership of the
address bus. Note that BR may be asserted for one or more cycles
and then deasserted due to an internal cancellation of the bus request
(for example, due to a load hit in the touch load buffer). See
Section 8.4.1, "Address Arbitration."
Negated—Indicates that the MPC8280 is not requesting the address
bus. The MPC8280 may have no bus operation pending, it may be
parked, or the ARTRY input was asserted on the previous bus clock
cycle.
is parked and the address bus is idle (BG asserted and ABB input
negated).
Negation—Occurs for at least one cycle following a qualified BG
even if another transaction is pending; also negated for at least one
cycle following any qualified ARTRY on the bus unless MPC8280
asserted ARTRY and requires a snoop copyback; may also be
negated if MPC8280 cancels the bus request internally before
receiving a qualified BG.
High Impedance—Occurs during a hard reset or checkstop condition
Chapter 7. 60x Signals
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Signal Descriptions
7-3