Motorola PowerQUICC II MPC8280 Series Reference Manual page 291

MPC8280
Latch &
A[0–31]
DRAM MUX
TSIZ[0–3]
DP[0–7]
Memory Control Signals
In single-MPC8280 bus mode, the MPC8280 uses the address
bus as a memory address bus. Slaves cannot use the 60x bus
signals because the addresses have memory timing, not address
tenure timing.
8.2.2 60x-Compatible Bus Mode
The 60x-compatible bus mode can include one or more potential external masters (for
example, an L2 cache, an ASIC DMA, a high-end processor that implements the PowerPC
architecture, or a second MPC8280). When operating in a multiprocessor configuration, the
MOTOROLA
Freescale Semiconductor, Inc.
APE
TS
TT[0–4]
TBST
CI
WT
GBL
AACK
ARTRY
DBG
D[0–63]
TA
TEA
Figure 8-1. Single-MPC8280 Bus Mode
NOTE
Chapter 8. The 60x Bus
For More Information On This Product,
Go to: www.freescale.com
Bus Configuration
I/O
MEM
8-3