Motorola PowerQUICC II MPC8280 Series Reference Manual page 294

60x Bus Protocol Overview
8.3.1 Arbitration Phase
The external bus design permits one device (either the MPC8280 or a bus-attached external
device) to be granted bus mastership at a time. Bus arbitration can be handled either by an
external central bus arbiter or by the internal on-chip arbiter. In the latter case, the system
is optimized for three external bus masters besides the MPC8280. The arbitration
configuration (external or internal) is determined at system reset by sampling configuration
pins. See Section 4.3.2.2, "60x Bus Arbiter Configuration Register (PPC_ACR)," for more
information.
The MPC8280 controls bus access through the bus request (BR) and bus grant (BG) signals.
It determines the state of the address and data bus busy signals by monitoring DBG, TS,
AACK, and TA, and it qualifies them with ABB and DBB.
The following signals are used for address bus arbitration:
• BR (bus request)—A device asserts BR to request address bus mastership.
• BG (bus grant)—Assertion indicates that a bus device may, with proper
qualification, assume mastership of the address bus. A qualified bus grant occurs
when BG is asserted while ABB and ARTRY are negated.
• ABB (address bus busy)—A device asserts ABB to indicate it is the current address
bus master. Note that if all devices assert ABB with TS and would normally negate
ABB after AACK is asserted, the devices can ignore ABB because the MPC8280
can internally generate ABB. The MPC8280's ABB, if enabled, must be tied to a
pull-up resistor.
The following signals are used for data bus arbitration:
• DBG (data bus grant)—Indicates that a bus device can, with the proper qualification,
assume data bus mastership. A qualified data bus grant occurs when DBG is asserted
while DBB and ARTRY are negated.
• DBB (data bus busy)—Assertion by the device indicates that the device is the
current data bus master. The device master always assumes data bus mastership if it
needs the data bus and is given a qualified data bus grant (see DBG). Note that if all
devices assert DBB in conjunction with qualified data bus grant and would normally
negate DBB after the last TA is asserted, the devices can ignore DBB because the
MPC8280 can generate DBB internally. The MPC8280's DBB signal, if enabled,
must be tied to a pull-up resistor.
The following is a summary of rules for arbitration:
• Preference among devices is determined at the request level. The MPC8280
supports eight levels of bus requests.
• When no bus device is requesting the address bus, the MPC8280 parks the device
selected in the arbiter configuration register on the bus.
8-6
Freescale Semiconductor, Inc.
MPC8280 PowerQUICC II Family Reference Manual
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