Motorola PowerQUICC II MPC8280 Series Reference Manual page 283

State Meaning
Timing Comments Assertion/Negation—Initial beat coincides with DBB, for bursts,
7.2.7.1.2 Data Bus (D[0–63])—Input
Following are the state meaning and timing comments for the D[0–63] input signals.
State Meaning
Timing Comments Assertion/Negation—Data must be valid on the same bus clock
7.2.7.2 Data Bus Parity (DP[0–7])
The eight data bus parity (DP[0–7]) signals both output and input signals.
7.2.7.2.1 Data Bus Parity (DP[0–7])—Output
Following are the state meaning and timing comments for the DP[0–7] output signals.
State Meaning
MOTOROLA
Freescale Semiconductor, Inc.
Asserted/Negated—Represents the state of data during a data write.
Byte lanes not selected for data transfer do not supply valid data.
MPC8280 duplicates data to enable valid data to be sent to different
port sizes.
transitions on the bus clock cycle following each assertion of TA
and, for port size, transitions on the bus clock cycle following each
assertion of PSDVAL.
High Impedance—Occurs on the bus clock cycle after the final
assertion of TA, TEA, or certain ARTRY cases.
Table 7-1. Data Bus Lane Assignments
Data Bus Signals
D0–D7
D8–D15
D16–D23
D24–D31
D32–D39
D40–D47
D48–D55
D56–D63
Asserted/Negated—Represents the state of data during a data read
transaction.
cycle that TA and/or PSDVAL is asserted.
Asserted/Negated—Represents odd parity for each of 8 bytes of data
write transactions. Odd parity means that an odd number of bits,
Chapter 7. 60x Signals
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Byte Lane
0
1
2
3
4
5
6
7
Signal Descriptions
7-15