Motorola PowerQUICC II MPC8280 Series Reference Manual page 258

Signal Descriptions
Signal
PSDVAL 60x data valid—(Input/output) Assertion of the PSDVAL pin indicates that a data beat is valid on
the data bus. The difference between the TA pin and the PSDVAL pin is that the TA pin is asserted
to indicate 60x data transfer terminations while the PSDVAL signal is asserted with each data
beat movement. Thus always when TA is asserted, PSDVAL will be asserted but when PSDVAL
is asserted, TA is not necessarily asserted. For example when a double word (2x64 bits) transfer
is initiated by the SDMA to a memory device that has 32 bits port size, PSDVAL will be asserted
3 times without TA and finally both pins will be asserted to terminate the transfer.
TA Transfer acknowledge—(Input/output) Indicates that a 60x data beat is valid on the data bus. For
60x single beat transfers, assertion of this pin indicates the termination of the transfer. For 60x
burst transfers TA is asserted four times to indicate the transfer of four data beats with the last
assertion indicating the termination of the burst transfer.
TEA Transfer error acknowledge—(Input/output) Assertion of this pin indicates a bus error. 60x
masters within the MPC8280 monitor the state of this pin. MPC8280's internal bus monitor may
assert this pin in case it identified a 60x bus transfer that is hung.
GBL Global—(Input/output) When a 60x master within the chip initiates a bus transaction it drives this
pin. When an external 60x master initiates a bus transaction it should drive this pin. Assertion of
this pin indicates that the transfer is global and it should be snooped by caches in the system.
The MPC8280's data cache monitors the state of this pin.
IRQ1 Interrupt request 1—This input is one of the eight external lines that can request (by means of the
internal interrupt controller) a service routine from the core.
CI Cache inhibit—Output pin. Used for L2 cache control. For each MPC8280 60x transaction
initiated in the core, the state of this pin indicates if this transaction should be cached or not.
Assertion of the CI pin indicates that the transaction should not be cached.
BADDR29 Burst address 29—There are five burst address output pins. These pins are outputs of the 60x
memory controller. These pins are used in external master configuration and are connected
directly to memory devices controlled by MPC8280's memory controller. For information on the
use of this signal, see Section 11.2.14, "BADDR[27:31] Signal Connections."
IRQ2 Interrupt request 2—This input is one of the eight external lines that can request (by means of the
internal interrupt controller) a service routine from the core.
WT Write through—Output used for L2 cache control. For each core-initiated MPC8280 60x
transaction, the state of this pin indicates if the transaction should be cached using write-through
or copy-back mode. Assertion of WT indicates that the transaction should be cached using the
write-through mode.
BADDR30 Burst address 30—There are five burst address output pins. These pins are outputs of the 60x
memory controller. These pins are used in external master configuration and are connected
directly to memory devices controlled by MPC8280's memory controller. For information on the
use of this signal, see Section 11.2.14, "BADDR[27:31] Signal Connections."
IRQ3 Interrupt request 3—This input is one of the eight external lines that can request (by means of the
internal interrupt controller) a service routine from the core.
6-6
Freescale Semiconductor, Inc.
Table 6-1. External Signals (continued)
MPC8280 PowerQUICC II Family Reference Manual
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