Motorola PowerQUICC II MPC8280 Series Reference Manual page 260

Signal Descriptions
Signal
BCTL0 Buffer control 0—Output whose function is controlling buffers on the 60x data bus. Usually used
with BCTL1 that is multiplexed on CS10. The exact function of this pin is defined by the value of
SIUMCR[BCTLC]. See Section 4.3.2.6, "SIU Module Configuration Register (SIUMCR)," for
details.
PWE[0–7] 60x bus write enable—Outputs of the 60x bus GPCM. These pins select byte lanes for write
operations.
PSDDQM[0–7] 60x bus SDRAM DQM—The DQM pins are outputs of the SDRAM control machine. These pins
select specific byte lanes of SDRAM devices.
PBS[0–7] 60x bus UPM byte select—The byte select pins are outputs of the UPM in the memory controller.
They are used to select specific byte lanes during memory operations. The timing of these pins
is programmed in the UPM. The actual driven value depends on the address and size of the
transaction and the port size of the accessed device.
PSDA10 60x bus SDRAM A10—(Output) from the 60x bus SDRAM controller. Part of the address when a
row address is driven and is part of the command when a column address is driven.
PGPL0 60x bus UPM general purpose line 0—One of six general purpose output lines from UPM. The
values and timing of this pin is programmed in the UPM.
PSDWE 60x bus SDRAM write enable—(Output) from the 60x bus SDRAM controller. Should be
connected to SDRAMs' WE input.
PGPL1 60x bus UPM general purpose line 1—One of six general purpose output lines from UPM. The
values and timing of this pin is programmed in the UPM.
POE 60x bus output enable—The output enable pin is an output of the 60x bus GPCM. Controls the
output buffer of memory devices during read operations.
PSDRAS 60x bus SDRAM ras—Output from the 60x bus SDRAM controller. Should be connected to
SDRAMs' RAS input.
PGPL2 60x bus UPM general purpose line 2—One of six general purpose output lines from UPM. The
values and timing of this pin is programmed in the UPM.
PSDCAS 60x bus SDRAM CAS—Output from the 60x bus SDRAM controller. Should be connected to
SDRAMs' CAS input.
PGPL3 60x bus UPM general purpose line 3—One of six general purpose output lines from UPM. The
values and timing of this pin is programmed in the UPM.
PGTA 60x GPCM TA—This input pin is used for transaction termination during GPCM operation.
Requires external pull up resistor for proper operation.
PUPMWAIT 60x bus UPM wait—This is an input to the UPM. An external device may hold this pin high to force
the UPM to wait until the device is ready for the continuation of the operation.
PGPL4 60x bus UPM general purpose line 4—One of six general purpose output lines from UPM. The
values and timing of this pin is programmed in the UPM.
PPBS 60x bus parity byte select—In systems in which data parity is stored in a separate chip, this output
is used as the byte-select for that chip.
6-8
Freescale Semiconductor, Inc.
Table 6-1. External Signals (continued)
MPC8280 PowerQUICC II Family Reference Manual
For More Information On This Product,
Go to: www.freescale.com
Description
MOTOROLA