ST STM32G4 Series Reference Manual page 1636

Advanced arm-based 32-bit mcus

Hide thumbs Also See for STM32G4 Series:

Table of Contents

Universal synchronous/asynchronous receiver transmitter (USART/UART)

USART receive data register (USART_RDR)

Address offset: 0x24

Reset value: 0xXXXX XXXX

Bits 31:9 Reserved, must be kept at reset value.

Bits 8:0 RDR[8:0]: Receive data value

USART transmit data register (USART_TDR)

Address offset: 0x28

Reset value: 0xXXXX XXXX

Bits 31:9 Reserved, must be kept at reset value.

Bits 8:0 TDR[8:0]: Transmit data value

Note: This register must be written only when TXE/TXFNF=1.

Contains the received data character.

The RDR register provides the parallel interface between the input shift register and the

internal bus (see

When receiving with the parity enabled, the value read in the MSB bit is the received parity

Contains the data character to be transmitted.

The USART_TDR register provides the parallel interface between the internal bus and the

output shift register (see

When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register),

the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect

because it is replaced by the parity.

RM0440 Rev 1

Chapters

Table of Contents

Do you have a question about the STM32G4 Series and is the answer not in the manual?