ST STM32G4 Series Reference Manual page 1604

Universal synchronous/asynchronous receiver transmitter (USART/UART)
36.7 USART registers
Refer to
36.7.1 USART control register 1 [alternate] (USART_CR1)
Address offset: 0x00
Reset value: 0x0000 0000
The same register can be used in FIFO mode enabled (this section) and FIFO mode
disabled (next section).
FIFO mode enabled
31 30 29 28
RXF FIFO
TXFEIE M1
FIE EN
rw rw rw rw
15 14 13 12
OVER8 CMIE MME M0
rw rw rw rw
Bit 31 RXFFIE: RXFIFO Full interrupt enable
This bit is set and cleared by software.
0: Interrupt inhibited
1: USART interrupt generated when RXFF=1 in the USART_ISR register
Bit 30 TXFEIE: TXFIFO empty interrupt enable
This bit is set and cleared by software.
0: Interrupt inhibited
1: USART interrupt generated when TXFE=1 in the USART_ISR register
Bit 29 FIFOEN: FIFO mode enable
This bit is set and cleared by software.
0: FIFO mode is disabled.
1: FIFO mode is enabled.
This bitfield can only be written when the USART is disabled (UE=0).
Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode
Bit 28 M1: Word length
This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or
cleared by software.
M[1:0] = '00': 1 start bit, 8 Data bits, n Stop bit
M[1:0] = '01': 1 start bit, 9 Data bits, n Stop bit
M[1:0] = '10': 1 start bit, 7 Data bits, n Stop bit
This bit can only be written when the USART is disabled (UE=0).
Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate
1604/2083
Section 1.2 on page 71
27 26 25
EOBIE RTOIE
rw rw rw
11 10 9
WAKE PCE PS
rw rw rw
and in Smartcard modes only. It must not be enabled in IrDA and LIN modes.
(0x7F and 0x55 frames detection) are not supported.
for a list of abbreviations used in register descriptions.
24 23 22
DEAT[4:0]
rw rw rw
8 7 6
PEIE TXFNFIE TCIE RXFNEIE IDLEIE
rw rw rw
RM0440 Rev 1
21 20 19 18
DEDT[4:0]
rw rw rw rw
5 4 3 2
TE RE
rw rw rw rw
RM0440
17 16
rw rw
1 0
UESM UE
rw rw