ST STM32G4 Series Reference Manual page 1657

RM0440
M bits
10
10
1. Legends: SB: start bit, STB: stop bit, PB: parity bit.
2. In the data register, the PB is always taking the MSB position (8th or 7th, depending on the M bit value).
Even parity
The parity bit is calculated to obtain an even number of "1s" inside the frame which is made
of the 6, 7 or 8 LSB bits (depending on M bit values) and the parity bit.
As an example, if data=00110101, and 4 bits are set, then the parity bit will be 0 if even
parity is selected (PS bit in LPUART_CR1 = 0).
Odd parity
The parity bit is calculated to obtain an odd number of "1s" inside the frame made of the 6, 7
or 8 LSB bits (depending on M bit values) and the parity bit.
As an example, if data=00110101 and 4 bits set, then the parity bit will be 1 if odd parity is
selected (PS bit in LPUART_CR1 = 1).
Parity checking in reception
If the parity check fails, the PE flag is set in the LPUART_ISR register and an interrupt is
generated if PEIE is set in the LPUART_CR1 register. The PE flag is cleared by software
writing 1 to the PECF in the LPUART_ICR register.
Parity generation in transmission
If the PCE bit is set in LPUART_CR1, then the MSB bit of the data written in the data
register is transmitted but is changed by the parity bit (even number of "1s" if even parity is
selected (PS=0) or an odd number of "1s" if odd parity is selected (PS=1)).
37.3.11 LPUART single-wire Half-duplex communication
Single-wire Half-duplex mode is selected by setting the HDSEL bit in the LPUART_CR3
register. In this mode, the following bits must be kept cleared:
•
LINEN and CLKEN bits in the LPUART_CR2 register,
•
SCEN and IREN bits in the LPUART_CR3 register.
The LPUART can be configured to follow a Single-wire Half-duplex protocol where the TX
and RX lines are internally connected. The selection between half- and Full-duplex
communication is made with a control bit HDSEL in LPUART_CR3.
As soon as HDSEL is written to '1':
• The TX and RX lines are internally connected.
•
The RX pin is no longer used
• The TX pin is always released when no data is transmitted. Thus, it acts as a standard
I/O in idle or in reception. It means that the I/O must be configured so that TX is
configured as alternate function open-drain with an external pull-up.
Low-power universal asynchronous receiver transmitter (LPUART)
Table 348: LPUART frame formats
PCE bit
0
1
RM0440 Rev 1
(1)
LPUART frame
| SB | 7bit data | STB |
| SB | 6-bit data | PB | STB |
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