RM0440
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:8 GT[7:0]: Guard time value
This bitfield is used to program the Guard time value in terms of number of baud clock
periods.
This is used in Smartcard mode. The Transmission Complete flag is set after this guard time
value.
This bitfield can only be written when the USART is disabled (UE=0).
Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value.
Bits 7:0 PSC[7:0]: Prescaler value
In IrDA low-power and normal IrDA mode:
PSC[7:0] = IrDA Normal and Low-Power Baud Rate
Used for programming the prescaler for dividing the USART source clock to achieve the low-
power frequency:
The source clock is divided by the value given in the register (8 significant bits):
00000000: Reserved - do not program this value
00000001: divides the source clock by 1
00000010: divides the source clock by 2
...
In Smartcard mode:
PSC[4:0]: Prescaler value
Used for programming the prescaler for dividing the USART source clock to provide the
Smartcard clock.
The value given in the register (5 significant bits) is multiplied by 2 to give the division factor
of the source clock frequency:
00000: Reserved - do not program this value
00001: divides the source clock by 2
00010: divides the source clock by 4
00011: divides the source clock by 6
...
This bitfield can only be written when the USART is disabled (UE=0).
Note: Bits [7:5] must be kept cleared if Smartcard mode is used.
36.7.7
USART receiver timeout register (USART_RTOR)
Address offset: 0x14
Reset value: 0x0000 0000
31
30
29
rw
rw
rw
15
14
13
rw
rw
rw
Universal synchronous/asynchronous receiver transmitter (USART/UART)
Refer to
Section 36.4: USART implementation on page
This bitfield is reserved and forced by hardware to '0' when the Smartcard and IrDA
modes are not supported. Refer to
28
27
26
25
BLEN[7:0]
rw
rw
rw
rw
12
11
10
9
rw
rw
rw
rw
Section 36.4: USART implementation on page
24
23
22
rw
rw
rw
8
7
6
RTO[15:0]
rw
rw
rw
RM0440 Rev 1
1554.
21
20
19
18
RTO[23:16]
rw
rw
rw
rw
5
4
3
2
rw
rw
rw
rw
1554.
17
16
rw
rw
1
0
rw
rw
1621/2083
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