ST STM32G4 Series Reference Manual page 1620

Universal synchronous/asynchronous receiver transmitter (USART/UART)
36.7.5 USART baud rate register (USART_BRR)
This register can only be written when the USART is disabled (UE=0). It may be
automatically updated by hardware in auto baud rate detection mode.
Address offset: 0x0C
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 BRR[15:0]: USART baud rate
36.7.6 USART guard time and prescaler register (USART_GTPR)
Address offset: 0x10
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
1620/2083
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
BRR[15:4]
BRR[15:4] = USARTDIV[15:4]
BRR[3:0]
When OVER8 = 0, BRR[3:0] = USARTDIV[3:0].
When OVER8 = 1:
BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right.
BRR[3] must be kept cleared.
28 27 26 25
Res. Res. Res.
12 11 10 9
GT[7:0]
rw rw rw rw
24 23 22
Res. Res. Res.
8 7 6
BRR[15:0]
rw rw rw
24 23 22
Res. Res. Res.
8 7 6
rw rw rw
RM0440 Rev 1
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
rw rw rw rw
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
PSC[7:0]
rw rw rw rw
RM0440
17 16
Res. Res.
1 0
rw rw
17 16
Res. Res.
1 0
rw rw