Clock Gating - NXP Semiconductors PN7462 series User Manual

NXP Semiconductors
The selection is done using the PCR_SELECT_SYSTEMCLOCK [2:0]
001 ... 20 MHz clkHFO
010 ... 24 MHz clkUSBPLL/2 (internal test purpose)
100 ... 27.12 MHz clkXtal
Others ... INVALID, should not be programmed

8.5 Clock Gating

In order to reduce the overall power consumption, the PN7462 family enables adjusting
the system clock and integrates clock gating mechanisms.
The clocks of the following blocks can be activated or deactivated, depending on the
peripherals used (see Fig 23):
• Contactless interface
• Contact interface
• Host interfaces
• I
• SPI master interface
• CRC engine
• Timers
• Random generator
• System Clock
• EEPROM
• Flash memory
To enable the clock for this part, the corresponding bit in PCR_CLK_CFG_REG and
PCR_CLK_CFG2_REG needs to be set.
UM10858
User manual
COMPANY PUBLIC
2
C master interface
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
(default)
(internal test purpose)
314514
UM10858
PN7462 family HW user manual
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