Table 9-2 Mpu Type Register Bit Assignments; Figure 9-1 Mpu Type Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

Memory Protection Unit
31
Field Name
[31:24] -
[23:16] IREGION
[15:8] DREGION
[7:0] -
[0] SEPARATE
9-4
Reset state
0x00000800
Figure 9-1 shows the fields of the MPU Type Register.
24 23
Reserved
Table 9-2 describes the fields of the MPU Type Register.
Definition
Reserved.
Because the processor core uses only a unified MPU, IREGION always contains
Number of supported MPU regions field. DREGION contains
contains an MPU indicating eight MPU regions, otherwise it contains
Reserved.
Because the processor core uses only a unified MPU, SEPARATE is always 0.
MPU Control Register
Use the MPU Control Register to:
• enable the MPU
• enable the default memory map (background region)
• enable the MPU when in Hard Fault, NMI, and FAULTMASK escalated handlers.
When the MPU is enabled, at least one region of the memory map must be enabled for
the MPU to function unless the PRIVDEFENA bit is set. If the PRIVDEFENA bit is set
and no regions are enabled, then only privileged code can operate.
When the MPU is disabled, the default address map is used, as if no MPU is present.
When the MPU is enabled, only the system partition and vector table loads are always
accessible. Other areas are accessible based on regions and whether PRIVDEFENA is
enabled.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
16 15
IREGION DREGION

Figure 9-1 MPU Type Register bit assignments

Table 9-2 MPU Type Register bit assignments

8 7 1 0
Reserved
SEPARATE
.
0x00
if the implementation
0x08
.
0x00
ARM DDI 0337B