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Bus Interface
14.9
Write buffer
14-12
To prevent bus wait cycles from stalling the Cortex-M3 processor during data stores,
buffered stores to the DCode and System buses go through a one-entry write buffer. If
the write buffer is full, subsequent accesses to the bus stall until the write buffer has
drained. The write buffer is only used if the bus waits the data phase of the buffered
store, otherwise the transaction completes on the bus.
DMB and DSB instructions wait for the write buffer to drain before completing. If an
interrupt comes in while DMB/DSB is waiting for the write buffer to drain, the opcode
after the DMB/DSB is returned to on the completion of the interrupt. This is because
interrupt processing is a memory barrier operation.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
ARM DDI 0337B
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