Table 13-7 Formatter And Flush Status Register Bit Assignments; Figure 13-6 Formatter And Flush Status Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

ARM DDI 0337B
Figure 13-6 shows the fields of the Formatter and Flush Status Register.

Figure 13-6 Formatter and Flush Status Register bit assignments

Table 13-7 describes the fields of the Formatter and Flush Status Register.

Table 13-7 Formatter and Flush Status Register bit assignments

Formatter and Flush Control Register
Use the Formatter and Flush Control Register to read whether the formatter is present
or not. This register is read only because dynamic control of the formatter is not
possible. If the formatter is present, the register reads
enabled and in continuous mode, with triggers indicated when TRIGIN is asserted.
The register address, access type, and Reset state are:
Address
0xE0040304
Access Read only
Reset state or
0x00 0x102
Formatter Synchronization Counter Register
The global synchronization trigger is generated by the PC Sampler block. This means
that there is no synchronization counter in the TPIU.
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Field Name Definition
[31:4] - Reserved
[3] FtNonStop Formatter cannot be stopped.
[2] TCPresent This bit always reads zero.
[1] FtStopped This bit always reads zero.
[0] FlInProg This bit always reads zero.
, indicating formatter
0x102
Trace Port Interface Unit
13-11