Table 12-14 Sw-Dp Register Map - ARM Cortex-M3 Technical Reference Manual

Address a
CTRLSEL
b00 X
b01 b0
b1
b10 X
b11 X
a. CTRLSEL bit in the SELECT register, see The AP Select Register, SELECT on page 12-57.
b. Entries in the Access column refer to whether the SWD protocol makes a read or a write access to the given address.
Debug Port (DP) register descriptions
12.5.3
ARM DDI 0337B
Table 12-14 shows the SW-DP register map.
Description
Access
ID Code R
Register
Abort Register W
DP R/W
Control/Status
Register
Wire Control R/W
Register
Read Resend R
Register
Select Register W
Read Buffer R
- W
This section gives a detailed description of each of the DP registers. Each description
states whether the register is implemented for the JTAG-DP and for the SW-DP, and any
differences in the implementation.
The Abort Register, ABORT
The Abort Register is always present on all DP implementations. Its main purpose is to
force a DAP abort, and on a SW-DP it is also used to clear error and sticky flag
conditions.
JTAG-DP It is at address
SW-DP It is at address 0b00 on write operations when the DPnAP bit =1, see Key
to illustrations of operations on page 12-22. Access to the Abort Register
is not affected by the value of the CTRLSEL bit in the Select Register.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
b Reference
The Identification Code Register, IDCODE on page 12-52
The Abort Register, ABORT
The Control/Status Register, CTRL/STAT on page 12-53
The Wire Control Register, WCR (SW-DP only) on page 12-60
The Read Resend Register, RESEND (SW-DP only) on page 12-62
The AP Select Register, SELECT on page 12-57
The Read Buffer, RDBUFF on page 12-59
-
when the Instruction Register (IR) contains ABORT.
0x0

Table 12-14 SW-DP register map

Debug Port
12-49