Table 5-15 Exception Subtype Transitions - ARM Cortex-M3 Technical Reference Manual

Exceptions
Intended
activation
subtype Triggering event
Thread Reset signal
ISR/NMI HW signal or set-pend
Monitor
Debug event
SVCall SVC instruction
PendSV Software pend request
UsageFault Undefined instruction
NoCpFault Access to absent CP
BusFault Memory access error
MemManage MPU mismatch
HardFault Escalation
FaultEscalate Escalate request from
Configurable fault
handler
a. While halting not enabled.
5-32
Table 5-15 shows exception subtype transitions.
Activation
Asynchronous
Asynchronous
a Synchronous
Synchronous
Chain
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Chain
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Table 5-15 Exception subtype transitions

Priority effect
Immediate, thread is lowest
Preempt or tail-chain according to priority
If priority less than or equal to current, hard fault
If priority less than or equal to current, hard fault
Preempt or tail-chain according to priority
If priority greater than or equal to current, hard fault
If priority greater than or equal to current, hard fault
If priority greater than or equal to current, hard fault
If priority greater than or equal to current, hard fault
Higher than all bus NMI
Boosts priority of local handler to same as hard fault so it can
return and chain to Configurable Fault handler
ARM DDI 0337B