Private Peripheral Bus Interface; Table A-9 Private Peripheral Bus Interface - ARM Cortex-M3 Technical Reference Manual

A.9

Private Peripheral Bus interface

Name Direction
PADDR[19:2] Output
PADDR31 Output
PSEL Output
PENABLE Output
PWDATA[31:0] Output
PWRITE Output
PRDATA[31:0] Input
PREADY Input
PSLVERR Input
ARM DDI 0337G
Unrestricted Access
Table A-9 lists the signals of the PPB interface.
Description
17-bit address. Only the bits that are relevant to the External Private Peripheral Bus are
driven.
This signal is driven HIGH when the AHB-AP is the requesting master. It is driven
LOW when DCore is the requesting master.
Indicates that a data transfer is requested.
Strobe to time all accesses. Indicates the second cycle of an APB transfer.
32-bit write data bus.
Write not read.
Read data bus.
APB slave ready.
APB slave error.
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Table A-9 Private Peripheral Bus interface

Non-Confidential
Signal Descriptions
A-11