Table 8-24 Usage Fault Status Register Bit Assignments; Figure 8-19 Usage Fault Status Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

Nested Vectored Interrupt Controller
Bits Field
[15-10] -
[9] DIVBYZERO
[8] UNALIGNED
[7:4] -
[3] NOCP
8-36
The register address, access type, and Reset state are:
Address
0xE000ED2A
Access Read/write clear
Reset state
0x00000000
Figure 8-19 shows the bit assignments of the Usage Fault Status Register.
Table 8-24 describes the bit assignments of the Usage Fault Status Register.
Function
Reserved
When DIV_0_TRP (see Configuration Control Register on page 8-26) is enabled and an
SDIV or UDIV instruction is used with a divisor of 0, this fault occurs The instruction is
executed and the return PC points to it. If DIV_0_TRP is not set, then the divide returns a
quotient of 0.
When UNALIGN_TRP is enabled (see Configuration Control Register on page 8-26), and
there is an attempt to make an unaligned memory access, then this fault occurs.
Unaligned LDM/STM/LDRD/STRD instructions always fault irrespective of the setting of
UNALIGN_TRP.
Reserved.
Attempt to use a coprocessor instruction. The processor does not support coprocessor
instructions.
Copyright © 2005-2008 ARM Limited. All rights reserved.
15
Reserved
DIVBYZERO
UNALIGNED

Figure 8-19 Usage Fault Status Register bit assignments

Table 8-24 Usage Fault Status Register bit assignments

Non-Confidential
7 4 3 2 1 0
10 9 8
Reserved
NOCP
INVPC
INVSTATE
UNDEFINSTR
ARM DDI 0337G
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