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Bus Interface
12.4
DCode bus interface
12.4.1
Exclusives
12.4.2
Memory attributes
12-6
The DCode interface is a 32-bit AHB-Lite bus. Data and debug accesses to Code
memory space (
0x00000000 - 0x1FFFFFFF
accesses have a higher priority than debug accesses. This means that debug accesses are
waited until core accesses have completed when there are simultaneous core and debug
access to this bus.
Control logic in this interface converts unaligned data and debug accesses into two or
three (depending on the size and alignment of the unaligned access) aligned accesses.
This stalls any subsequent data or debug access until the unaligned access has
completed.
See Access alignment on page 12-11 for a description of unaligned accesses.
Note
It is strongly recommended that any external arbitration between the ICode and DCode
AHB bus interfaces ensures that DCode has a higher priority than ICode.
The DCode bus supports exclusive accesses. This is carried out using two sideband
signals, EXREQD and EXRESPD. For more information, see DCode interface on
page A-9.
For more information about semaphores and the local exclusive monitor see the ARM
Architecture Memory Model chapter in the ARMv7M ARM Architecture Reference
Manual.
All DCode memory accesses are marked as cacheable and non-bufferable,
HPROTD[3:2] = 2'b10, and as allocate and non-shareable, MEMATTRD = 2'b01.
These attributes are hard wired. If an MPU is fitted, the MPU region attributes are
ignored for the DCode bus.
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) are performed over this bus. Core data
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