Table 8-28 Bus Fault Address Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

Bits Field
[31:0] ADDRESS
ARM DDI 0337G
Unrestricted Access
Bus Fault Address Register
Use the Bus Fault Address Register to read the address of the location that generated a
Bus Fault.
The register address, access type, and Reset state are:
Address
E000ED38
Access Read/write
Reset state Unpredictable
Table 8-28 describes the bit assignments of the Bus Fault Address Register.
Function
Bus fault address field. ADDRESS is the data address of a faulted load or store attempt. When an
unaligned access faults, the address is the address requested by the instruction, even if that is not
the address that faulted. Flags in the Bus Fault Status Register indicate the cause of the fault. See
Bus Fault Status Register on page 8-34.
Auxiliary Fault Status Register
Use the Auxiliary Fault Status Register (AFSR) to determine additional system fault
information to software.
The AFSR flags map directly onto the AUXFAULT inputs of the processor, and a
single-cycle high level on an external pin causes the corresponding AFSR bit to become
latched as one. The bit can only be cleared by writing a one to the corresponding AFSR
bit.
When an AFSR bit is written or latched as one, an exception does not occur. If you
require an exception, you must use an interrupt.
The register address, access type, and Reset state are:
Address
0xE000ED3C
Access Read/write-clear
Reset state 0x00000000
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Table 8-28 Bus Fault Address Register bit assignments

Non-Confidential
Nested Vectored Interrupt Controller
8-41