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A.7
DCode interface
Name
Direction
HADDRD[31:0]
Output
HTRANSD[1:0]
Output
HWRITED
Output
HSIZED[2:0]
Output
HBURSTD[2:0]
Output
HPROTD[3:0]
Output
EXREQD
Output
MEMATTRD[1:0]
Output
HMASTERD[1:0]
Output
HWDATAD[31:0]
Output
HREADYD
Input
HRESPD[1:0]
Input
HRDATAD[31:0]
Input
EXRESPD
Input
ARM DDI 0337G
Unrestricted Access
Table A-7 lists the signals of the DCode interface.
Description
32-bit data address bus
Indicates whether the current transfer is IDLE, NONSEQUENTIAL, or
SEQUENTIAL.
Write not read
Indicates the size of the access. Can be 8, 16, or 32 bits.
Indicates if the transfer is part of a burst. Data accesses are performed as INCR on
Cortex-M3.
Provides information on the access. Always indicates cacheable and non-bufferable
on this bus.
Exclusive request.
Memory attributes.
Always 01 for this bus (non-shareable, allocate).
Indicates the current DCode bus master:
•
0 = Core data side accesses.
•
1 = DAP accesses.
•
2 = Core instruction side accesses. These include vector fetches that are
marked as data by HPROTD[0]. This value cannot appear on HMASTERD.
•
3 = Reserved. This value cannot appear on HMASTERD.
32-bit write data bus.
When HIGH indicates that a transfer has completed on the bus. This signal is driven
LOW to extend a transfer.
The transfer response status. OKAY or ERROR.
Read data.
Exclusive response.
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Signal Descriptions
Table A-7 DCode interface
A-9
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