Table 11-3 Comp Mapping - ARM Cortex-M3 Technical Reference Manual

ARM DDI 0337B
Flash Patch Remap Register
Use the Flash Patch Remap Register to provide the location in System space where a
matched address is remapped. The REMAP address is 8-word aligned, with one word
allocated to each of the eight FPB comparators.
A comparison match remaps to:
{3'b001, REMAP, COMP[2:0], HADDR[1:0]}
where:
• 3'b001 hardwires the remapped access to system space
• REMAP is the 24-bit, 8-word aligned remap address
• COMP is the matching comparator. See Table 11-3.
• HADDR[1:0] is the two LSBs of the original address. HADDR[1:0] is always
2'b00 for instruction fetches.
The register address, access type, and Reset state are:
Address
0xE0002004
Access Read/write
Reset state This register is not reset
Figure 11-3 shows the fields of the Flash Patch Remap Register.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
COMP[2:0] Comparator
000 FP_COMP0
001 FP_COMP1
010 FP_COMP2
011 FP_COMP3
100 FP_COMP4
101 FP_COMP5
110 FP_COMP6
111 FP_COMP7
System Debug

Table 11-3 COMP mapping

Description
Instruction comparator
Instruction comparator
Instruction comparator
Instruction comparator
Instruction comparator
Instruction comparator
Literal comparator
Literal comparator
11-9