Table 11-7 Dwt Control Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

Field Name
[31:28] NUMCOMP
[27:23] -
[22] CYCEVTEN
[21] FOLDEVTENA
[20] LSUEVTENA
[19] SLEEPEVTENA
[18] EXCEVTENA
ARM DDI 0337B
Table 11-7 describes the fields of the DWT Control Register.
Definition
Number of comparators field. This read-only field contains b0100 to indicate four
comparators.
Reserved. Read As Zero. Write ignore.
Enables Cycle count event. Emits an event when the POSTCNT counter triggers it. See
CYCTAP (bit [9]) and POSTPRESET (bits [4:1]) for details.
1 = Cycle count events enabled
0 = Cycle count events disabled.
This event is only be emitted if PCSAMPLENA (bit [12]) is disabled.
PCSAMPLENA overrides the setting of this bit.
Reset clears the CYCEVTENA bit.
Enables Folded instruction count event. Emits an event when DWT_FOLDCNT
overflows (every 256 cycles of folded instructions). A folded instruction is one which
does not incur even one cycle to execute (e.g. an IT instruction is folded away and so does
not use up one cycle).
1 = Folded instruction count events enabled
0 = Folded instruction count events disabled
Reset clears the FOLDEVTENA bit.
Enables LSU count event. Emits an event when DWT_LSUCNT overflows (every 256
cycles of LSU operation). LSU counts include all LSU costs after the initial cycle for the
instruction.
1 = LSU count events enabled
0 = LSU count events disabled
Reset clears the LSUEVTENA bit.
Enables Sleep count event. Emits an event when DWT_SLEEPCNT overflows (every
256 cycles that the processor is sleeping).
1 = Sleep count events enabled
0 = Sleep count events disabled
Reset clears the SLEEPEVTENA bit.
Enables Interrupt overhead event. Emits an event when DWT_EXCCNT overflows
(every 256 cycles of interrupt overhead).
1 = Interrupt overhead event enabled
0 = Interrupt overhead event disabled
Reset clears the EXCEVTENA bit.
Copyright © 2005, 2006 ARM Limited. All rights reserved.

Table 11-7 DWT Control Register bit assignments

System Debug
11-15