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Exceptions
5.9
Resets
Action
NVIC resets, holds core in reset
NVIC releases core from reset
Core sets stack
Core sets PC and LR
Reset routine runs
5.9.1
Vector Table and Reset
5-20
The NVIC is reset at the same time as the core and controls the release of reset into the
core. As a result, the behavior of reset is predictable. Table 5-7 shows the reset behavior.
Description
NVIC clears most of its registers. The processor is in Thread mode, priority is
privileged, and the stack is set to Main.
NVIC releases core from reset.
Core reads the start SP, SP_main, from vector-table offset 0.
Core reads the start PC from vector-table offset. LR is set to
NVIC has interrupts disabled, and NMI and Hard Fault are not disabled.
For more information about resets, see Chapter 6 Clocking and Resets.
The vector table at location 0 provides the vector table at reset. It must contain at least
four values:
•
stack top address
•
reset routine location
•
NMI ISR location
•
Hard Fault ISR location.
When interrupts are enabled, the vector table regardless of location, points to all
mask-enabled exceptions. Also, the SVCall ISR location is populated if the SVC
instruction is used.
An example of a full vector table:
unsigned int stack_base[STACK_SIZE];
void ResetISR(void);
void NmiISR(void);
...
ISR_VECTOR_TABLE vector_table_at_0
{
stack_base + sizeof(stack_base),
ResetISR,
NmiSR,
FaultISR,
Copyright © 2005-2008 ARM Limited. All rights reserved.
Non-Confidential
Table 5-7 Reset actions
.
0xFFFFFFFF
ARM DDI 0337G
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