Table 5-3 Priority Grouping - ARM Cortex-M3 Technical Reference Manual

Exceptions
Interrupt priority level field, PRI_N[7:0]
Binary point
PRIGROUP[2:0] position
b000 bxxxxxxx.y
b001 bxxxxxx.yy
b010 bxxxxx.yyy
b011 bxxxx.yyyy
b100 bxxx.yyyyy
b101 bxx.yyyyyy
b110 bx.yyyyyyy
b111 b.yyyyyyyy
5-8
Table 5-3 shows how writing to PRIGROUP splits an eight bit PRI_N field into a
pre-emption priority field (x) and a subpriority field (y).
Pre-emption field
[7:1]
[7:2]
[7:3]
[7:4]
[7:5]
[7:6]
[7]
None
Note
• Table 5-3 shows the priorities for the processor configured with eight bits of
priority.
• For a processor configured with less than eight bits of priority, the lower bits of
the register are always 0. For example, if four bits of priority are implemented,
PRI_N[7:4] sets the priority, and PRI_N[3:0] is 4'b0000.
An interrupt can pre-empt another interrupt in progress only if its pre-emption priority
is higher than that of the interrupt in progress.
For more information on priority optimizations, priority level grouping, and priority
masking, see the ARMv7-M Architecture Reference Manual.
Copyright © 2005-2008 ARM Limited. All rights reserved.
Subpriority field
[0]
[1:0]
[2:0]
[3:0]
[4:0]
[5:0]
[6:0]
[7:0]
Non-Confidential

Table 5-3 Priority grouping

Number of
pre-emption Number of
priorities subpriorities
128 2
64 4
32 8
16 16
8 32
4 64
2 128
0 256
ARM DDI 0337G
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