Figure 8-6 Interrupt Priority Registers 0-31 Bit Assignments - ARM Cortex-M3 Technical Reference Manual

Nested Vectored Interrupt Controller
8-16
The priority registers are stored with the most significant bit (MSB) first. This means
that if there are four bits of priority, the priority value is stored in bits [7:4] of the byte.
However, if there are three bits of priority, the priority value is stored in bits [7:5] of the
byte. This means that an application can work even if it does not know how many
priorities are possible.
The register address, access type, and Reset state are:
Address
0xE000E400
Access Read/write
Reset state
0x00000000
Figure 8-6 shows the fields of Interrupt Priority Registers 0-7.
The lower PRI_n bits can specify subpriorities for priority grouping. See Exception
priority on page 5-5.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
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0xE000E41F

Figure 8-6 Interrupt Priority Registers 0-31 bit assignments

ARM DDI 0337B