Table 11-22 Itm Trace Control Register Bit Assignments; Figure 11-14 Itm Trace Control Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

System Debug
31
Bits Field
[31:24] -
[23] BUSY
[22:16] ATBID
[15:10] -
11-34
ITM Trace Control Register
Use this register to configure and control ITM transfers.
Note
You can only write to this register in privilege mode.
The register address, access type, and Reset state are:
Access Read/write
Address 0xE0000E80
Reset
0x00000000
Figure 11-14 shows the ITM Control Register bit assignments.
24 23 22
Reserved
BUSY
Table 11-22 describes the bit assignments of the ITM Control Register.
Function
0b00000000.
Set when ITM events present and being drained
ATB ID for CoreSight system.
0b000000.
Copyright © 2005-2008 ARM Limited. All rights reserved.
15
16
ATBID Reserved

Figure 11-14 ITM Trace Control Register bit assignments

Table 11-22 ITM Trace Control Register bit assignments

Non-Confidential
7
10 9 8
TSPrescale
Reserved
SWOENA
DWTENA
SYNCENA
TSENA
ITMENA
2 1
5 4 3 0
ARM DDI 0337G
Unrestricted Access