Figure 9-2 Mpu Control Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

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ARM DDI 0337G

Unrestricted Access

Unless HFNMIENA is set, the MPU is not enabled when the exception priority is –1 or

–2. These priorities are only possible when in Hard fault, NMI, or when FAULTMASK

is enabled. The HFNMIENA bit enables the MPU when operating with these two

The register address, access type, and Reset state are:

Figure 9-2 shows the bit assignments of the MPU Control Register.

Figure 9-2 MPU Control Register bit assignments

Non-Confidential

Memory Protection Unit