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Embedded Trace Macrocell
15.2
Data tracing
15-6
The Cortex-M3 system can perform low-bandwidth data tracing using the Data
Watchpoint and Trace (DWT) and Instruction Trace Macrocell (ITM) components. To
enable instruction trace to be supported with a low pin-count, data trace is not included
in the ETM. This results in a considerable saving in gate count for the ETM, because
the triggering resources can be simplified.
When the ETM is implemented in processor, the two trace sources (ITM and ETM) both
feed into the Trace Port Interface Unit (TPIU), where they are combined and usually
output over the trace port. DWT is able to provide either focused data trace, or global
data trace (subject to FIFO overflow issues). The TPIU is optimized for the
requirements of a single core Cortex-M3 system.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
ARM DDI 0337B
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