Table of Contents
Advertisement
15.2
CPU ETM interface port descriptions
Port name
ETMIVALID
ETMIBRANCH
ETMIINDBR
ETMDVALID
ETMICCFAIL
ETMINTSTAT[2:0]
ETMINTNUM[8:0]
ARM DDI 0337G
Unrestricted Access
The processor has a port that enables the ETM to determine the instruction execution
sequence. These port descriptions are described in Table 15-1.
Direction
Qualified by
Output
No qualifier
Output
ETMIVALID
Output
ETMIBRANCH
Output
No qualifier
Output
ETMIVALID
Output
No qualifier
Output
ETMINTSTAT
Copyright © 2005-2008 ARM Limited. All rights reserved.
Description
Instruction in execute is valid. Marks that an opcode has
entered the first cycle of execute.
Opcode is a branch target. Marks that current code is the
destination of a Program Counter (PC) modifying event
(branch, interrupt processing).
Opcode branch target is indirect. Marks that the current
opcode is a branch target whose destination the PC
contents cannot deduce. For example, LSU, register
move, or interrupt processing.
Signals that the current data address as seen by the Data
Watchpoint and Trace (DWT) is valid on this cycle.
Opcode condition code fail or pass. Marks if the current
opcode has failed or passed its conditional execution
check. An opcode is conditionally executed if it is a
conditional branch, or for all other opcode found in an IT
block.
Interrupt status. Marks the interrupt status of the current
cycle:
000 no status
001 interrupt entry
010 interrupt exit
011 interrupt return
100 - Vector fetch and stack push. ETMINTSTAT
Entry/Return is asserted in the first cycle of the new
interrupt context. Exit occurs without ETMIVALID.
Interrupt number. Marks the interrupt number of the
current execution context.
Non-Confidential
Embedded Trace Macrocell Interface
Table 15-1 ETM interface ports
15-3
Advertisement
Table of Contents
