Table 8-29 Auxiliary Fault Status Register Bit Assignments; Table 8-30 Software Trigger Interrupt Register Bit Assignments; Figure 8-22 Software Trigger Interrupt Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

Nested Vectored Interrupt Controller
Bits Field Function
[31:0] IMPDEF Implementation defined. The bits map directly onto the signal assignment to the AUXFAULT inputs.
See Miscellaneous on page A-4.
31
Bits Field Function
[31:9] - Reserved.
[8:0] INTID Interrupt ID field. Writing a value to the INTID field is the same as manually pending an interrupt by
setting the corresponding interrupt bit in an Interrupt Set Pending Register.
8-42
describes the field of the AFSR.
Software Trigger Interrupt Register
Use the Software Trigger Interrupt Register to pend an interrupt to trigger.
The register address, access type, and Reset state are:
Address
0xE000EF00
Access Write-only
Reset state
0x00000000
Figure 8-22 shows the bit assignments of the Software Trigger Interrupt Register.
Reserved

Figure 8-22 Software Trigger Interrupt Register bit assignments

Table 8-30 describes the bit assignments of the Software Trigger Interrupt Register.

Table 8-30 Software Trigger Interrupt Register bit assignments

Copyright © 2005-2008 ARM Limited. All rights reserved.

Table 8-29 Auxiliary Fault Status Register bit assignments

Non-Confidential
9 8
INTID
ARM DDI 0337G
Unrestricted Access
0