Table 8-25 Debug Fault Status Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

Field Name
[31:5] -
[4] EXTERNAL
[3] VCATCH
[2] DWTTRAP
[1] BKPT
[0] HALTED
ARM DDI 0337B
Table 8-25 describes the fields of the Debug Fault Status Register.
Definition
Reserved
External debug request flag:
1 = EDBGRQ signal asserted
0 = EDBGRQ signal not asserted.
The processor stops on next instruction boundary.
Vector catch flag:
1 = vector catch occurred
0 = no vector catch occurred.
When the VCATCH flag is set, a flag in one of the local fault status registers is also set to
indicate the type of fault.
Data Watchpoint and Trace (DWT) flag:
1 = DWT match
0 = no DWT match.
The processor stops at the current instruction or at the next instruction.
BKPT flag:
1 = BKPT instruction execution
0 = no BKPT instruction execution.
The BKPT flag is set by a BKPT instruction in flash patch code, and also by normal code.
Return PC points to breakpoint containing instruction.
Halt request flag:
1 = halt requested by NVIC, including step. The processor is halted on the next instruction.
0 = no halt request.
Memory Manage Fault Address Register
Use the Memory Manage Fault Address Register to read the address of the location that
caused a Memory Manage Fault.
The register address, access type, and Reset state are:
Address
0xE000ED34
Access Read/write
Reset state Unpredictable
Copyright © 2005, 2006 ARM Limited. All rights reserved.

Table 8-25 Debug Fault Status Register bit assignments

Nested Vectored Interrupt Controller
8-37