Tpiu Registers; Table 17-5 Tpiu Registers - ARM Cortex-M3 Technical Reference Manual

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Table of Contents

Trace Port Interface Unit

TPIU registers

Summary of the TPIU registers

Name of register

Supported Sync Port Sizes Register

Current Sync Port Size Register

Async Clock Prescaler Register

Selected Pin Protocol Register

Formatter and Flush Status Register

Formatter and Flush Control Register

Formatter Synchronization Counter Register

Integration Register: TRIGGER

Integration Register: ITATBCTR2

Integration Register: ITATBCTR0

Integration Mode Control Register

Integration register : FIFO data 0

Integration register : FIFO data 1

Claim tag set register

Claim tag clear register

This section describes the TPIU registers. It contains the following:

Summary of the TPIU registers

Description of the TPIU registers on page 17-9.

Table 17-5 provides a summary of the TPIU registers.

You can configure any of the TPIU registers to be present or not present. Any register

that is configured as not present reads as zero.

ARM DDI 0337G