Nvic Programmer's Model; Table 8-1 Nvic Registers - ARM Cortex-M3 Technical Reference Manual

8.2

NVIC programmer's model

8.2.1 NVIC register map
Name of register
Interrupt Control Type Register
SysTick Control and Status Register
SysTick Reload Value Register
SysTick Current Value Register
SysTick Calibration Value Register
Irq 0 to 31 Set Enable Register
.
.
.
Irq 224 to 239 Set Enable Register
Irq 0 to 31 Clear Enable Register
ARM DDI 0337B
This section lists and describes the NVIC registers. It contains the following:
• NVIC register map
• NVIC register descriptions on page 8-7.
Table 8-1 lists the NVIC registers. The NVIC space also implements System Control
Registers. The NVIC space is split as follows:
•
0xE000E000 - 0xE000E00F
• 0xE000E010 - 0xE000E0FF
•
0xE000E100 - 0xE000ECFF
•
0xE000ED00 - 0xE000ED8F
— CPUID
— System control, configuration, and status
— Fault Reporting
•
0xE000EF00 - 0xE000EF0F
•
0xE000EFD0 - 0xE000EFFF.
Type
Read-only
Read/write
Read/write
Read/write clear
Read/write
.
.
.
Read/write
Read/write
Copyright © 2005, 2006 ARM Limited. All rights reserved.
. Interrupt Type Register
. System Timer
. NVIC
. System Control Block, including:
. Software Trigger Exception Register
ID space.
Read-only
Nested Vectored Interrupt Controller

Table 8-1 NVIC registers

Reset
Address
value
0xE000E004
a
0xE000E010
0x00000000
0xE000E014
Unpredictable
0xE000E018
Unpredictable
0xE000E01C
STCALIB
0xE000E100
0x00000000
. .
. .
. .
0xE000E11C
0x00000000
0xE000E180
0x00000000
Page
page 8-7
page 8-8
page 8-9
page 8-10
page 8-11
page 8-12
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.
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page 8-12
page 8-13
8-3